EP3SL110F1152C2N Datasheet, PDF (292/341 Pages) Altera Corporation – Stratix III Device Handbook,

1–282
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–129 and Table 1–130 list the EP3SE110 regional clock (RCLK) adder values
that must be added to the GCLK values. Use these adder values to determine I/O
timing when the I/O pin is driven using the regional clock. This applies to all I/O
standards supported by Stratix III devices.
Table 1–129 lists the EP3SE110 column pin delay adders when using the regional
clock.
Table 1–129. EP3SE110 Column Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.111
2.506
-0.281
-2.121
0.14
2.513
-0.062
-1.833
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.19 0.103 0.105 0.103 0.177 0.085 0.101 0.098 0.146 ns
3.782 4.081 4.579 4.381 4.923 4.222 4.603 4.401 4.984 ns
-0.079 -0.074 -0.074 -0.072 -0.128 0.056 0.051 0.054 -0.055 ns
-2.75 -2.908 -3.127 -3.057 -3.165 -2.959 -3.157 -2.903 -3.172 ns
Table 1–130 lists the EP3SE110 row pin delay adders when using the regional clock.
Table 1–130. EP3SE110 Row Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
-0.003
0.116
0.02
-0.103
-0.002
0.122
0.019
-0.105
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
0.001 -0.012 -0.01 -0.017 0.078 -0.02 -0.02 -0.016 0.08 ns
0.192 0.212 0.227 0.217 0.375 0.198 0.219 0.209 0.379 ns
0.027 0.041 0.044 0.048 -0.038 0.051 0.057 0.051 -0.04 ns
-0.162 -0.179 -0.194 -0.185 -0.322 -0.167 -0.183 -0.175 -0.324 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation