EP3SL110F1152C2N Datasheet, PDF (19/341 Pages) Altera Corporation – Stratix III Device Handbook,

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–9
Electrical Characteristics
Internal Weak Pull-Up Resistor
Table 1–12 lists the weak pull-up resistor values for Stratix III devices.
Table 1–12. Internal Weak Pull-Up Resistor for Stratix III Devices (Note 1), (3)
Symbol
Parameter
Conditions
Min Typ Max Unit
Value of the I/O pin pull- ^{VCCIO = 3.3 V ± 5% (2)}
—
25
—
k
up resistor before and VCCIO = 3.0 V ± 5% (2)
—
25
—
k
R_PU
during configuration, as
well as user mode if the
V_CCIO = 2.5 V ± 5% (2)
programmable pull-up ^{VCCIO = 1.8 V ± 5% (2)}
—
25
—
k
—
25
—
k
resistor option is
enabled
V_CCIO = 1.5 V ± 5% (2)
V_CCIO = 1.2 V ± 5% (2)
—
25
—
k
—
25
—
k
Notes to Table 1–12:
(1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins.
(2) Pin pull-up resistance values may be lower if an external source drives the pin higher than V_CCIO.
(3) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak
pull-down resistor is approximately 25k .
I/O Standard Specifications
The following tables list input voltage sensitivities (V_IH and V_IL), output voltages
(V_OH and V_OL), and current drive characteristics (I_OH and I_OL) for all I/O standards
supported by Stratix III devices. V_OL and V_OH values are valid at the corresponding
I_OL and I_OH, respectively.
Table 1–13 through Table 1–18 list the Stratix III device family I/O standard
specifications. Refer to “Glossary” on page 1–326 for an explanation of terms used in
the Table 1–14 through Table 1–18.
Table 1–13. Single-Ended I/O Standards Specifications
I/O Standard
V_CCIO (V)
V_IL (V)
Min Typ Max Min Max
3.3-V LVTTL 3.135 3.3 3.465 -0.3
0.8
3.0-V LVTTL 2.85 3 3.15 -0.3
0.8
3.3-V LVCMOS 3.135 3.3 3.465 -0.3
0.8
3.0-V LVCMOS 2.85 3 3.15 -0.3
0.8
2.5 2.625 -0.3
0.7
2.5-V LVTTL/
LVCMOS
2.375 2.5 2.625 -0.3
0.7
2.5 2.625 -0.3
0.7
1.8-V LVTTL /
LVCMOS
1.71
1.8
1.89 -0.3 0.35 * V_CCIO
1.5-V LVTTL/
LVCMOS
1.425 1.5 1.575 -0.3 0.35 * V_CCIO
1.2-V LVTTL /
LVCMOS
1.14
1.2
1.26 -0.3 0.35 * V_CCIO
3.0-V PCI
3.0-V PCI-X
2.85
3
3.15 — 0.3 * V_CCIO
2.85
3
3.15 — 0.35 * V_CCIO
V_IH (V)
Min
Max
1.7
3.6
1.7
3.6
1.7
3.6
1.7
3.6
1.7
3.6
1.7
3.6
1.7
3.6
0.65 * V_CCIO V_CCIO + 0.3
0.65 * V_CCIO V_CCIO + 0.3
0.65 * V_CCIO
0.5 * V_CCIO
0.5 * V_CCIO
V_CCIO + 0.3
3.6
—
V_OL (V)
Max
0.4
0.4
0.2
0.2
0.2
0.4
0.7
0.45
V_OH (V)
Min
2.4
2.4
V_CCIO - 0.2
V_CCIO - 0.2
2.1
2
1.7
V_CCIO - 0.45
0.25 * V_CCIO 0.75 * V_CCIO
0.25 * V_CCIO 0.75 * V_CCIO
0.1 * V_CCIO
0.1 * V_CCIO
0.9 * V_CCIO
0.9 * V_CCIO
IOL
(mA)
2
2
0.1
0.1
0.1
1
2
2
2
2
1.5
1.5
IOH
(mA)
-2
-2
-0.1
-0.1
-0.1
-1
-2
-2
-2
-2
-0.5
-0.5
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2