EP3SL110F1152C2N Datasheet, PDF (60/341 Pages) Altera Corporation – Stratix III Device Handbook,

1–50
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–43. EP3SL50 Column Pins output Timing Parameters (Part 7 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
4mA _GCLK
PLL ^tco
GCLK t_co
6mA _GCLK
PLL ^tco
1.2-V
HSTL
CLASS I
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
10mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
1.2-V
HSTL
CLASS II
GCLK t_co
16mA _GCLK
PLL ^tco
3.0-V PCI
GCLK t_co
— _GCLK
PLL ^tco
3.0-V
PCI-X
GCLK t_co
— _GCLK
PLL ^tco
3.015
3.371
3.007
3.363
3.008
3.364
2.997
3.353
2.997
3.353
3.018
3.374
3.121
3.477
3.121
3.477
3.003
3.371
2.995
3.363
2.996
3.364
2.985
3.353
2.985
3.353
3.006
3.374
3.109
3.477
3.109
3.477
4.256 4.625 5.101 4.983 5.185 4.625 5.101 4.983 5.185 ns
4.778 5.187 5.711 5.568 5.835 5.187 5.711 5.568 5.835 ns
4.247 4.616 5.092 4.974 5.176 4.616 5.092 4.974 5.176 ns
4.769 5.178 5.702 5.559 5.826 5.178 5.702 5.559 5.826 ns
4.254 4.624 5.101 4.983 5.185 4.624 5.101 4.983 5.185 ns
4.777 5.186 5.711 5.568 5.835 5.186 5.711 5.568 5.835 ns
4.241 4.611 5.087 4.969 5.171 4.611 5.087 4.969 5.171 ns
4.764 5.173 5.697 5.554 5.821 5.173 5.697 5.554 5.821 ns
4.241 4.611 5.088 4.970 5.172 4.611 5.088 4.970 5.172 ns
4.764 5.173 5.698 5.555 5.822 5.173 5.698 5.555 5.822 ns
4.257 4.626 5.101 4.983 5.185 4.626 5.101 4.983 5.185 ns
4.780 5.188 5.711 5.568 5.835 5.188 5.711 5.568 5.835 ns
4.302 4.660 5.126 5.008 5.210 4.660 5.126 5.008 5.210 ns
4.825 5.222 5.736 5.593 5.860 5.222 5.736 5.593 5.860 ns
4.302 4.660 5.126 5.008 5.210 4.660 5.126 5.008 5.210 ns
4.825 5.222 5.736 5.593 5.860 5.222 5.736 5.593 5.860 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation