EP3SL110F1152C2N Datasheet, PDF (22/341 Pages) Altera Corporation – Stratix III Device Handbook,

1–12
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–18. Differential I/O Standard Specifications (Part 2 of 2)
I/O
Standard
V_CCIO (V)
V_ID (V) (1)
V_ICM(DC) (V)
Min Typ Max Min Condition Max Min Condition Max
V_OD (V) (2)
Min Typ Max
V_OCM (V) (2)
Min Typ Max
2.5 V LVDS ^{2.375 2.5 2.625 0.1 VCM = 1.25}
—
0.05
(6)
D_max 700
Mbps
1.8
(6)
0.247 —
0.6
(Column I/O)
2.375 2.5 2.625 0.1 V_CM = 1.25
—
1.05
(6)
D > _max 700
Mbps
1.55
(6)
0.247
—
0.6
1.0 1.25 1.5
1.0 1.25 1.5
RSDS
(Row I/O)
2.375 2.5 2.625 0.1 V_CM = 1.25
— 0.3
—
1.4 0.1 0.2 0.6 0.5 1.2 1.4
RSDS
(Column I/O)
2.375
2.5
2.625
0.1
V_CM = 1.25
— 0.3
—
1.4 0.1 0.2 0.6 0.5 1.2 1.5
Mini-LVDS
(Row I/O)
2.375 2.5 2.625 0.2
—
0.6 0.4
—
1.325 0.25 — 0.6 0.5 1.2 1.4
Mini-LVDS
(Column I/0)
2.375
2.5
2.625
0.2
—
0.6 0.4
—
1.325 0.25 — 0.6 0.5 1.2 1.5
LVPECL
2.375
(5)
2.5
(5)
2.625
(5)
0.3
—
(3)
2.375
(5)
2.5
(5)
2.625
(5)
0.3
—
—
0.6 ^{Dmax 700}
Mbps
1.8
(4)
——
—
—
1.0
D > _max 700
1.6
——
—
Mbps
(4)
———
———
Notes to Table 1–18:
(1) The minimum V_ID value is applicable over the entire common mode range, V_CM.
(2) RL range: 90 RL  110 .
(3) Column and row I/O banks support LVPECL I/O standards for input operation only on dedicated clock input pins. Differential clock inputs in column I/O use
V_{CC_CLKIN} that must be powered by 2.5 V. Differential clock inputs in row I/O banks are powered by V_CCPD.
(4) The receiver voltage input range for the data rate when D_max > 700 Mbps is 0.85 V V_IN 1.75 V.
The receiver voltage input range for the data rate when D_max 700 Mbps is 0.45 V V_IN 1.95 V.
(5) Power supply for the column I/O LVPECL differential clock input buffer is V_{CC_CLKIN}.
(6) The receiver voltage input range for the data rate when D_max > 700 Mbps is 1.0 V V_IN 1.6 V.
The receiver voltage input range for the data rate when D_max 700 Mbps is zero V V_IN 1.85 V.
Power Consumption
Altera offers two ways to estimate power for a design: the Excel-based Early Power
Estimator (EPE) and the Quartus^ II PowerPlay Power Analyzer feature.
The interactive Excel-based Early Power Estimator is typically used prior to designing
the FPGA in order to get a magnitude estimate of the device power. The Quartus II
PowerPlay Power Analyzer provides estimation based on the specifics of the design
after place-and-route is complete. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities
which, when combined with detailed circuit models, can yield very accurate power
estimation.
Refer to Table 1–4 on page 1–5 for supply current estimates for V_CCPGM and V . _{CC_CLKIN}
Use the EPE and PowerPlay Power Analyzer for current estimates of remaining
power supplies.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide For Stratix III FPGAs and the PowerPlay Power Analysis chapter in
the Quartus II Handbook.
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation