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EP3SL110F1152C2N Datasheet, PDF (35/341 Pages) Altera Corporation – Stratix III Device Handbook, | |||
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
1â25
Figure 1â3 shows the LVDS Soft-CDR/ DPA sinusoidal jitter tolerance specifications
for Stratix III devices.
Figure 1â3. LVDS Soft-CDR/DPA Sinusiodal Jitter Tolerance Specification for Stratix III Devices
Table 1â27 lists the LVDS Soft-CDR/ DPA sinusiodal jitter mask values for Stratix III
devices.
Table 1â27. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for Stratix III Devices
Jitter Frequency (Hz)
F1
10,000
F2
17,565
F3
1,493,000
F4
50,000,000
Jitter Amplitude
Unit
25.000
UI
25.000
UI
0.350
UI
0.350
UI
External Memory Interface Specifications
The following sections describe the external memory I/O timing specifications and
the DLL and DQS block specifications.
f For more information about the maximum clock rate support for external memory
interfaces with a half-rate or full-rate controller, refer to Section III: System Performance
Specifications of the External Memory Interfaces Handbook.
External Memory I/O Timing Specifications
Table 1â28 and Table 1â29 list Stratix III device timing uncertainties on the read and
write data paths. Use these specifications to determine timing margins for source
synchronous paths between the Stratix III FPGA and the external memory device. For
more information, refer to the figure for âSW (sampling window)â in the âGlossaryâ
on page 1â326.
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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