EP3SL110F1152C2N Datasheet, PDF (244/341 Pages) Altera Corporation – Stratix III Device Handbook,

1–234
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–113 lists the EP3SE80 column pins output timing parameters for single-ended
I/O standards.
Table 1–113. EP3SE80 Column Pins Output Timing Parameters (Part 1 of 7)
I/O
Standard
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
4mA
GCLK
PLL
t_co
3.559
3.859
3.559
3.865
4.935 5.323 5.638 5.693 5.865 5.323 5.638 5.693 5.865 ns
5.394 5.826 6.396 6.210 6.631 5.826 6.396 6.210 6.631 ns
3.3-V
LVTTL
GCLK t_co
8mA
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
3.442
3.792
3.347
3.706
3.442
3.798
3.347
3.712
4.781 5.161 5.525 5.523 5.752 5.161 5.525 5.523 5.752 ns
5.285 5.715 6.283 6.097 6.518 5.715 6.283 6.097 6.518 ns
4.644 5.018 5.433 5.371 5.660 5.018 5.433 5.371 5.660 ns
5.181 5.616 6.191 6.005 6.426 5.616 6.191 6.005 6.426 ns
GCLK t_co
16mA
GCLK
PLL
t_co
3.302
3.699
3.302
3.705
4.619 4.994 5.392 5.346 5.619 4.994 5.392 5.346 5.619 ns
5.164 5.588 6.150 5.964 6.385 5.588 6.150 5.964 6.385 ns
GCLK t_co
4mA
GCLK
PLL
t_co
3.562
3.865
3.562
3.871
4.939 5.335 5.645 5.707 5.872 5.335 5.645 5.707 5.872 ns
5.398 5.831 6.403 6.217 6.638 5.831 6.403 6.217 6.638 ns
3.3-V
LVCMOS
GCLK t_co
8mA
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
3.362
3.710
3.305
3.717
3.362
3.716
3.305
3.723
4.649 5.023 5.444 5.377 5.671 5.023 5.444 5.377 5.671 ns
5.191 5.633 6.202 6.016 6.437 5.633 6.202 6.016 6.437 ns
4.612 4.992 5.418 5.346 5.645 4.992 5.418 5.346 5.645 ns
5.185 5.612 6.176 5.990 6.411 5.612 6.176 5.990 6.411 ns
GCLK t_co
16mA
GCLK
PLL
t_co
3.285
3.701
3.285
3.707
4.558 4.934 5.389 5.289 5.616 4.934 5.389 5.289 5.616 ns
5.163 5.587 6.147 5.961 6.382 5.587 6.147 5.961 6.382 ns
GCLK t_co
4mA
GCLK
PLL
t_co
3.504
3.823
3.504
3.829
4.884 5.274 5.605 5.658 5.832 5.274 5.605 5.658 5.832 ns
5.361 5.794 6.363 6.177 6.598 5.794 6.363 6.177 6.598 ns
3.0-V
LVTTL
GCLK t_co
8mA
GCLK
PLL
t_co
GCLK t_co
12mA
GCLK
PLL
t_co
3.374
3.712
3.299
3.676
3.374
3.718
3.299
3.682
4.715 5.102 5.468 5.497 5.693 5.102 5.468 5.497 5.693 ns
5.231 5.660 6.225 6.041 6.459 5.660 6.225 6.041 6.459 ns
4.626 5.003 5.394 5.395 5.620 5.003 5.394 5.395 5.620 ns
5.168 5.591 6.151 5.967 6.386 5.591 6.151 5.967 6.386 ns
GCLK t_co
16mA
GCLK
PLL
t_co
3.262
3.658
3.262
3.664
4.561 4.934 5.365 5.345 5.592 4.934 5.365 5.345 5.592 ns
5.139 5.563 6.123 5.937 6.358 5.563 6.123 5.937 6.358 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation