EP3SL110F1152C2N Datasheet, PDF (38/341 Pages) Altera Corporation – Stratix III Device Handbook,

1–28
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Table 1–29. Transmitter Channel-to-Channel Skew (TCCS)—Write Side (Note 1) (Part 2 of 2)
C2
C3, I3
C4, I4
C4L, I4L
C4L, I4L
Memory Type
I/O
Standard
Width
V_CCL = 1.1 V
TCCS (ps)
V_CCL = 1.1 V
TCCS (ps)
V_CCL = 1.1 V
TCCS (ps)
V_CCL = 1.1 V
TCCS (ps)
V_CCL = 0.9 V
TCCS (ps)
Lead Lag Lead Lag Lead Lag Lead Lag Lead Lag
QDRII/II+ SRAM
1.8-V
HSTL
×9, ×18, 259 276 260 385 280 418 280 418 380 518
×36
QDRII/II+ SRAM
Emulation (2)
1.8-V
HSTL
×36
279 296 280 405 300 438 300 438 400 538
RLDRAM II
1.5-V
HSTL
×9, ×18 290 278 292 388 315 421 315 421 415 521
RLDRAM II
1.8-V
HSTL
×9, ×18 259 276 260 385 280 418 280 418 380 518
Notes to Table 1–29:
(1) The values apply to Column I/Os, Row I/Os, and Hybrid mode interfaces. Column I/Os refer to top and bottom I/Os. Hybrid mode refers to DQ/DQS groups
wrapping over Column I/Os and Row I/Os of the device.
(2) For implementation, refer to the “Supporting ×36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages” section in the External Memory
Interfaces in Stratix III Devices chapter.
DLL and DQS Logic Block Specifications
Table 1–30 lists the DLL frequency range specifications for Stratix III devices.
Table 1–30. DLL Frequency Range Specifications for Stratix III Devices
Frequency
Mode
Frequency Range (MHz)
Available Phase Shift
C2
C3, I3
C4, I4 C4L, I4L
0
90 – 150 90 – 140 90 – 120 90 – 120 22.5°, 45°, 67.5°, 90°
1
120 – 200 120 – 190 120 – 170 120 – 170 30°, 60°, 90°, 120°
2
150 – 240 150 – 230 150 – 200 150 – 200 36°, 72°, 108°, 144°
3
180 – 300 180 – 290 180 – 250 180 – 250 45°, 90°,135°, 180°
4
240 – 370 240 – 350 240 – 310 240 – 310 30°, 60°, 90°,120°
5
290 – 450 290 – 420 290 – 370 290 – 370 36°, 72°, 108°, 144°
6
360 – 560 360 – 530 360 – 460 360 – 460 45°, 90°, 135°, 180°
7
470 – 740 470 – 700 470 – 610 470 – 610 60°, 120°, 180°, 240°
Note to Table 1–30:
(1) “Low” indicates a 6-bit DQS delay setting; “high” indicates a 5-bit DQS delay setting.
Number of
DQS Delay
Delay Chains Buffer Mode (1)
16
Low
12
Low
10
Low
8
Low
12
High
10
High
8
High
6
High
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation