EP3SL110F1152C2N Datasheet, PDF (316/341 Pages) Altera Corporation – Stratix III Device Handbook,

1–306
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–138 lists the EP3SE260 row pins output timing parameters for differential I/O
standards.
Table 1–138. EP3SE260 Row Pins Output Timing Parameters (Part 1 of 3)
I/O Standard
LVDS
—
LVDS_E_1R —
LVDS_E_3R —
MINI-LVDS —
MINI-
LVDS_E_1R
—
MINI-
LVDS_E_3R
—
RSDS
—
RSDS_E_1R —
RSDS_E_3R —
4mA
DIFFERENTIAL
1.2-V
6mA
HSTL CLASS I
8mA
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
GCLK
PLL ^tco
3.152
3.536
3.376
3.812
4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 ns
5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 ns
GCLK t_co
GCLK
PLL ^tco
3.518
3.152
3.802
3.376
5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 ns
4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 ns
GCLK t_co
GCLK
PLL ^tco
3.536
3.518
3.812
3.802
5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 ns
5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 ns
GCLK t_co
GCLK
PLL ^tco
3.152
3.536
3.376
3.812
4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 ns
5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 ns
GCLK t_co
GCLK
PLL ^tco
3.518
3.562
3.802
3.845
5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 ns
5.678 5.894 6.468 6.301 6.680 6.046 6.621 6.301 6.680 ns
GCLK t_co
GCLK
PLL ^tco
3.548
3.544
3.831
3.827
5.665 5.881 6.455 6.288 6.667 6.032 6.608 6.288 6.667 ns
5.663 5.881 6.456 6.289 6.668 6.032 6.610 6.289 6.668 ns
GCLK t_co
GCLK
PLL ^tco
3.560
3.549
3.842
3.832
5.664 5.878 6.450 6.283 6.662 6.029 6.603 6.283 6.662 ns
5.660 5.874 6.447 6.280 6.659 6.026 6.600 6.280 6.659 ns
GCLK t_co
GCLK
PLL ^tco
3.546
3.557
3.829
3.839
5.658 5.872 6.445 6.278 6.657 6.024 6.599 6.278 6.657 ns
5.659 5.873 6.444 6.277 6.656 6.023 6.597 6.277 6.656 ns
GCLK t_co
GCLK
PLL ^tco
3.547
3.533
3.830
3.816
5.657 5.871 6.443 6.276 6.655 6.023 6.597 6.276 6.655 ns
5.642 5.856 6.429 6.262 6.641 6.008 6.582 6.262 6.641 ns
GCLK t_co
GCLK
PLL ^tco
3.530
3.527
3.812
3.810
5.638 5.852 6.425 6.258 6.637 6.004 6.578 6.258 6.637 ns
5.639 5.855 6.428 6.261 6.640 6.007 6.582 6.261 6.640 ns
GCLK t_co
GCLK
PLL ^tco
3.528
3.577
3.810
3.863
5.629 5.843 6.415 6.248 6.627 5.994 6.568 6.248 6.627 ns
5.700 5.916 6.491 6.324 6.703 6.068 6.644 6.324 6.703 ns
GCLK t_co
GCLK
PLL ^tco
3.553
3.535
3.839
3.820
5.682 5.899 6.474 6.307 6.686 6.051 6.629 6.307 6.686 ns
5.660 5.877 6.452 6.285 6.664 6.029 6.607 6.285 6.664 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation