EP3SL110F1152C2N Datasheet, PDF (69/341 Pages) Altera Corporation – Stratix III Device Handbook,

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–59
Table 1–47 lists the EP3SL50 column pins output timing parameters for differential
I/O standards.
Table 1–47. EP3SL50 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
LVDS_E_1R
GCLK t_co
—
GCLK
PLL
t_co
LVDS_E_3R
GCLK t_co
—
GCLK
PLL
t_co
MINI-
LVDS_E_1R
GCLK t_co
—
GCLK
PLL
t_co
MINI-
LVDS_E_3R
GCLK t_co
—
GCLK
PLL
t_co
RSDS_E_1R
GCLK t_co
—
GCLK
PLL
t_co
RSDS_E_3R
GCLK t_co
—
GCLK
PLL
t_co
GCLK t_co
4mA
GCLK
PLL
t_co
GCLK t_co
6mA
GCLK
PLL
t_co
DIFFERENTIAL
1.2-V HSTL
GCLK t_co
CLASS I
8mA
GCLK
PLL
t_co
GCLK t_co
10mA _GCLK
PLL
t_co
GCLK t_co
12mA _GCLK
PLL
t_co
DIFFERENTIAL
GCLK t_co
1.2-V HSTL
CLASS II
16mA _GCLK
PLL
t_co
3.029
3.025
3.029
3.025
3.029
3.025
3.056
3.046
3.046
3.039
3.038
3.060
3.050
3.045
3.043
3.035
3.036
3.035
3.047
3.043
3.033
3.031
3.031
3.035
3.246
3.249
3.246
3.249
3.246
3.249
3.279
3.269
3.269
3.263
3.261
3.283
3.272
3.268
3.266
3.257
3.259
3.256
3.269
3.266
3.255
3.253
3.254
3.257
4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 ns
4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 ns
4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 ns
4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 ns
4.575 4.976 5.487 5.347 5.565 5.101 5.612 5.474 5.631 ns
4.622 5.031 5.549 5.409 5.627 5.160 5.678 5.540 5.697 ns
4.646 5.054 5.571 5.431 5.649 5.181 5.698 5.560 5.717 ns
4.636 5.043 5.561 5.421 5.639 5.170 5.688 5.550 5.707 ns
4.639 5.047 5.565 5.425 5.643 5.175 5.693 5.555 5.712 ns
4.632 5.041 5.559 5.419 5.637 5.168 5.687 5.549 5.706 ns
4.629 5.038 5.556 5.416 5.634 5.165 5.683 5.545 5.702 ns
4.650 5.058 5.575 5.435 5.653 5.185 5.703 5.565 5.722 ns
4.629 5.035 5.550 5.410 5.628 5.161 5.676 5.538 5.695 ns
4.629 5.035 5.551 5.411 5.629 5.162 5.678 5.540 5.697 ns
4.628 5.034 5.549 5.409 5.627 5.161 5.677 5.539 5.696 ns
4.618 5.024 5.540 5.400 5.618 5.151 5.667 5.529 5.686 ns
4.624 5.031 5.548 5.408 5.626 5.159 5.676 5.538 5.695 ns
4.607 5.012 5.526 5.386 5.604 5.138 5.652 5.514 5.671 ns
4.625 5.030 5.544 5.404 5.622 5.157 5.671 5.533 5.690 ns
4.626 5.032 5.548 5.408 5.626 5.159 5.675 5.537 5.694 ns
4.615 5.021 5.536 5.396 5.614 5.148 5.663 5.525 5.682 ns
4.613 5.018 5.534 5.394 5.612 5.146 5.661 5.523 5.680 ns
4.616 5.023 5.539 5.399 5.617 5.150 5.667 5.529 5.686 ns
4.613 5.018 5.533 5.393 5.611 5.145 5.660 5.522 5.679 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2