EP3SL110F1152C2N Datasheet, PDF (109/341 Pages) Altera Corporation – Stratix III Device Handbook,

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–99
Table 1–63. EP3SL110 Column Pins Output Timing Parameters (Part 2 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 3.445
4mA
GCLK
PLL ^tco
3.835
3.445
3.835
4.773 5.150 5.645 5.514 5.808 5.150 5.645 5.514 5.808 ns
5.348 5.783 6.333 6.175 6.557 5.783 6.333 6.175 6.557 ns
3.3-V
LVCMOS
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.290
3.680
3.297
3.687
3.290
3.680
3.297
3.687
4.566 4.953 5.444 5.313 5.607 4.953 5.444 5.313 5.607 ns
5.141 5.585 6.132 5.974 6.356 5.585 6.132 5.974 6.356 ns
4.560 4.932 5.418 5.287 5.581 4.932 5.418 5.287 5.581 ns
5.135 5.564 6.106 5.948 6.330 5.564 6.106 5.948 6.330 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.281
3.671
3.281
3.671
4.537 4.906 5.389 5.258 5.552 4.906 5.389 5.258 5.552 ns
5.113 5.539 6.077 5.919 6.301 5.539 6.077 5.919 6.301 ns
GCLK t_co 3.403
4mA
GCLK
PLL ^tco
3.793
3.403
3.793
4.735 5.114 5.605 5.474 5.768 5.114 5.605 5.474 5.768 ns
5.311 5.746 6.293 6.135 6.517 5.746 6.293 6.135 6.517 ns
3.0-V
LVTTL
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.292
3.682
3.256
3.646
3.292
3.682
3.256
3.646
4.605 4.980 5.467 5.337 5.629 4.980 5.467 5.337 5.629 ns
5.181 5.612 6.156 5.999 6.379 5.612 6.156 5.999 6.379 ns
4.542 4.911 5.393 5.263 5.556 4.911 5.393 5.263 5.556 ns
5.118 5.543 6.082 5.925 6.305 5.543 6.082 5.925 6.305 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.238
3.628
3.238
3.628
4.513 4.883 5.365 5.234 5.528 4.883 5.365 5.234 5.528 ns
5.089 5.515 6.053 5.895 6.277 5.515 6.053 5.895 6.277 ns
GCLK t_co 3.317
4mA
GCLK
PLL ^tco
3.707
3.317
3.707
4.639 5.013 5.502 5.372 5.664 5.013 5.502 5.372 5.664 ns
5.215 5.646 6.191 6.034 6.414 5.646 6.191 6.034 6.414 ns
3.0-V
LVCMOS
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.238
3.628
3.233
3.623
3.238
3.628
3.233
3.623
4.516 4.884 5.367 5.237 5.529 4.884 5.367 5.237 5.529 ns
5.091 5.517 6.056 5.899 6.279 5.517 6.056 5.899 6.279 ns
4.508 4.877 5.359 5.228 5.522 4.877 5.359 5.228 5.522 ns
5.084 5.510 6.047 5.889 6.271 5.510 6.047 5.889 6.271 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.224
3.614
3.224
3.614
4.494 4.862 5.344 5.213 5.507 4.862 5.344 5.213 5.507 ns
5.070 5.495 6.032 5.874 6.256 5.495 6.032 5.874 6.256 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2