AK4950 Datasheet, PDF (97/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
■ Digital MIC Input (Stereo)
ADRST bit
(Addr:01H, D23)
X
1
(1)
IVL7-0 bits
(Addr:20H)
ALC Control 1
(Addr:24H )
ALC Control 2
(Addr:26H)
ALC Control 3
(Addr:27H)
Digital Filter Path
(Addr:2CH)
Filter Select1
(Addr:2DH)
COEW bit
(Addr:0DH, D16)
Filter Co-ef
(Addr:03H,04H,06H
Control Data MSB = 'L')
ALC State
XXH
XXH
(2)
(3)
XXH
(4)
XXH
(5)
XXH
(6)
XXH
0
(7)
(8)
XXH
(9)
ALC Disable
E1H
E1H
30H
59H
19H
(14)
17H
10H
1
0FD82DH (Addr: 03H)
FD27D4H (Addr : 04H)
0FB05BH (Addr : 06H)
ALC Enable
ALC Disable
PMPFIL bi
(Addr:00H, D23
Control Data MSB = 'H')
(10)
(13)
Digital MIC
(Addr:09H)
SDTO pin
State
00H
0 data Output
37H
1059/fs
(11)
07H
(12)
Norm al
Data Output
0 data output
Example:
Control I/F = 3-wire
PLL Master Mode (MCKO output)
Audio I/F Format: MSB justified
Sampling Frequency: 48kHz
Digital MIC setting:
Data is latched on the DMCLK failing edge
ALC setting:Refer to Table 34
HPF2: fc=150Hz, ADRST bit = “0”
(1) Addr:01H, Data:0BH
(2) Addr:20H, Data:E1H
(3) Addr:24H, Data:E1H
(4) Addr:26H, Data:30H
(5) Addr:27H, Data:59H
(6) Addr:2CH, Data:17H
(7) Addr:2CH, Data:17H
(8) Addr:0DH, Data:01H
(9) Addr:03H, Data:0FD82DH
Addr:04H, Data:FD27D4H
Addr:06H , Data:0FB05BH
(10) Addr:00H, Data:80H
(11) Addr:09H, Data:37H
Recording
(12) Addr:09H, Data:07H
(13) Addr:00H, Data:00H
(14) Addr:27H, Data:19H
Figure 71. Digital MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=48kHz. If the parameter of the ALC1 is changed, please refer to
the Figure 39. At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up ADRST bit (initializing cycle) setting (Addr = 01H)
(2) Set up ALC starting IVOL value. (Addr = 20H)
(3) Set up IREF value. (Addr = 24H)
(4) Set up RFST1-0 and WTM1-0 bits for ALC (Addr= 26H)
(5) Set up LMTH1-0, RGAIN2-0 bits and ALC bit. (Addr=27H)
(6) Set up Programmable Filter Path: PFSDO bit = ADCPF bit = “1” (Addr=2CH)
(7) Switch ON/OFF of the Programmable Filter: HPF bit = “1” (Addr= 2DH)
(8) Set up COEW bit = “1” (Addr = 0DH)
When COEW bit = “1”, registers on the register map 1 and 2 can be accessed. Set the most significant bit
(MSB) of the control data to “1” (Figure 52) to access registers on the register map 1, and set “0” to access
registers on the register map 2 (Figure 53).
(9) Set up Coefficient of the Programmable Filter (Addr=03H, 04H, 06H: Control data MSB = “L”)
(10) Power up of the Programmable Filter: (PMADL=PMADR=PMPFIL bits = “0” → “1”)
(11) Power up and set the digital MIC: (PMDMR=PMDML bits = “0” → “1”)
The initialization cycle of the ADC is 1059/fs=22.06ms@fs=48kHz when ADRST bit = “0”. ADC outputs “0”
during the initialization. ALC starts operation at the value set by IVOL (4).
(12) Power-down the digital MIC. PMDMR=PMDML bits “1” → “0”
(13) Programmable Filter Power-down ALC Disable: PMPFIL bit “1” → “0”
(14) ALC1 Disable: ALC1 bit = “1” → “0”
MS1320-E-00
- 97 -
2011/10