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| AK4950 Datasheet, PDF (26/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP | |||
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[AK4950]
â PLL Unlock State
1) PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
In this mode, the LRCK and BICK pins go to âLâ, and irregular frequency clock is output from the MCKO pin when
MCKO bit is â1â before the PLL goes to lock state after PMPLL bit = â0â â â1â. If MCKO bit is â0â, the MCKO pin
outputs âLâ (Table 7).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
The BICK and LRCK pins do not output irregular frequency clocks such as PLL unlock state by setting PMPLL bit to
â0â. During PMPLL bit = â0â, these pins output the same clocks as EXT Master Mode.
PLL State
MCKO pin
BICK pin
MCKO bit = â0â MCKO bit = â1â
LRCK pin
After PMPLL bit â0â â â1â
âLâ Output
Invalid
âLâ Output
âLâ Output
PLL Unlock (except the case above) âLâ Output
Invalid
Invalid
Invalid
PLL Lock
âLâ Output
Table 9
Table 10
1fs Output
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
2) PLL Slave Mode (PMPLL bit = â1â, M/S bit = â0â)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = â0â â
â1â. Then, the clock selected by Table 9 is output from the MCKO pin when PLL is locked. ADC and DAC output invalid
data when the PLL is unlocked. The DAC outputs can be muted by setting DACL and DACS bits to â0â.
PLL State
MCKO pin
MCKO bit = â0â MCKO bit = â1â
After PMPLL bit â0â â â1â
âLâ Output
Invalid
PLL Unlock (except the case above) âLâ Output
Invalid
PLL Lock
âLâ Output
Output
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = â0â, M/S bit = â0â)
MS1320-E-00
- 26 -
2011/10
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