AK4950 Datasheet, PDF (76/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
■ Register Definitions
Addr Register Name
D23
D22
00H Power Management 1 PMPFIL
0
R/W
R/W
R
Default
0
0
D21
PMBP
R/W
0
D20
PMSPK
R/W
0
D19
PMLO
R/W
0
D18
PMDAC
R/W
0
D17
PMADR
R/W
0
D16
PMADL
R/W
0
PMADL: MIC-Amp Lch and ADC Lch Power Management
0: Power-down (default)
1: Power-up
PMADR: MIC-Amp Rch, ADC Rch Power Management
0: Power down (default)
1: Power up
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz, ADRST bit = “0”) starts. After initializing, digital data of the ADC is output.
PMDAC: DAC Power Management
0: Power-down (default)
1: Power-up
PMLO: Stereo Line Output Power Management
0: Power-down (default)
1: Power-up
PMSPK: Speaker-Amp Power Management
0: Power-down (default)
1: Power-up
PMBP: Mono Input Power Management
0: Power-down (default)
1: Power-up
The ROUT/MIN pin performs as MIN pin. BEEPL and BEEPS bits control the path settings of Rch lineout
and speaker from the MIN pin respectively.
PMPFIL: Programmable Filter Block (HPF2/LPF/FIL3/EQ/5 Band EQ/ALC) Power Management
(DSP system reset)
0: Power down (default)
1: Power up
All blocks except regulators can be powered-down by writing “0” to the address “00H”, PMPLL, PMMP, PMDML,
PMDMR, DMPE, PMADR, PMV, PMCP and MCKO bits. In this case, register values are maintained.
MS1320-E-00
- 76 -
2011/10