AK4950 Datasheet, PDF (58/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
■ Stereo Line Output (LOUT, ROUT pin)
When PMBP bit = “0”, PMLO bit= “1” and DACL bit is set to “1”, L and R channel signals of DAC are output in
single-ended format from the LOUT and ROUT pins. When DACL bit is “0”, output signals are muted and LOUT and
ROUT pins output common voltage. The load impedance is 10kΩ (min.). When the PMLO bit = LOPS bit = “0”, the
stereo line output enters power-down mode and the output is pulled-down to VSS1 by 100kΩ(typ). When the LOPS bit is
“1”, stereo line output enters power-save mode. Pop noise at power-up/down can be reduced by changing PMLO bit when
LOPS bit = “1”. In this case, output signal line should be pulled-down by 20kΩ after AC coupled as Figure 42. Rise/Fall
time is 300ms (max) if C=1μF and R_L=10kΩ. When PMLO bit = “1” and LOPS bit = “0”, stereo line output is in normal
operation.
LOVL1-0 bits set the gain of stereo line output.
LOPS
0
1
“DACL bit” “LOVL1-0 bits”
DAC
LOUT pin
ROUT pin
Figure 41. Stereo Line Output
PMLO
Mode
LOUT/ROUT pin
0
Power Down
Pull-down to VSS1
1
Normal Operation
Normal Operation
0
Power Save
Fall down to VSS1
1
Power Save
Rise up to
Common Voltage
Table 42. Stereo Line Output Mode Select
(default)
LOVL1-0 bits
AVDD
Gain
00
2.7 ~ 3.6 V
0dB
01
3.0 ~ 3.6 V +1.34dB (default)
10
2.7 ~ 3.6 V
+2dB
11
3.0 ~ 3.6 V +3.34dB
Table 43. Stereo Lineout Volume Setting
LOUT 1μF
ROUT
220Ω
20kΩ
Figure 42. External Circuit for Stereo Line Output (in case of using a Pop Noise Reduction Circuit)
MS1320-E-00
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2011/10