AK4950 Datasheet, PDF (100/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
■ Mono Output Signal from Speaker
CLOCK
Clocks can be stopped.
PMBP bit
(Addr:00H, D21)
(1)
(5)
PMSPK bit
(Addr:00H, D20)
Example:
(1) Addr:00H, Data:30H
(2) Addr:04H, Data: 08H
BEEPS bit
(Addr:04H, D19)
SPPSN bit
(Addr:04H, D23)
SPP pin
SPN pin
(2)
(6)
(3)
(4)
Hi-Z
Normal Output
Hi-Z
Hi-Z
AVDD/2 Normal Output AVDD/2 Hi-Z
Mono Signal Output
(3) Addr:04H, Data:D23
(4) Addr:00H, Data:00H
(5) Addr:04H, Data:00H
Figure 74. “MIN-Amp Æ Speaker-Amp” Output Sequence
<Example>
When only the path of “MIN-Amp → SRK-Amp” is in operation, the clocks are not needed.
(1) Power up MIN-Amp and Speaker-Amp: PMBP = PMSPK bits = “0” → “1”
(2) Disable the path of “DAC → SPK-Amp”: DACS bit = “0”
Enable the path of “MIN → SPK-Amp”: BEEPS bit = “0” → “1”
(3) Exit power-save mode of SPK-Amp: SPPSN bit = “0” → “1”
This period should be set in accordance with the time constant of the capacitor (C) and resistor (R) connected
to the MIN pin. Pop noise may occur if the SPK-Amp output is enabled before the MIN-Amp input is
stabilized. e.g. R=33kΩ, C=0.1μF: Recommended waiting time is 5τ = 16.5ms or more.
(4) Enter power-save mode of the SPK-Amp: SPPSN bit = “1” → “0”
(5) Power down MIN-Amp and SPK-Amp: PMBP = PMSPK bits = “1” → “0”
(6) Disable the path of “MIN → SPK-Amp”: BEEPS bit = “1” → “0”
MS1320-E-00
- 100 -
2011/10