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AK4950 Datasheet, PDF (16/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP
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[AK4950]
Parameter
Symbol min
typ
max Unit
Audio Interface Timing
Master Mode
BICK “↓” to LRCK Edge (Note 26)
LRCK Edge to SDTO (MSB)
(Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
Slave Mode
LRCK Edge to BICK “↑” (Note 26)
BICK “↑” to LRCK Edge (Note 26)
LRCK Edge to SDTO (MSB)
(Except I2S mode)
BICK “↓” to SDTO
SDTI Hold Time
SDTI Setup Time
tMBLR
−40
-
40
ns
tLRD
−70
-
70
ns
tBSD
−70
-
70
ns
tSDH
50
-
-
ns
tSDS
50
-
-
ns
tLRB
50
-
-
ns
tBLR
50
-
-
ns
tLRD
-
-
80
ns
tBSD
-
-
80
ns
tSDH
50
-
-
ns
tSDS
50
-
-
ns
Control Interface Timing (3-wire Mode):
CCLK Period
tCCK
200
-
-
ns
CCLK Pulse Width Low
tCCKL
80
-
-
ns
Pulse Width High
tCCKH
80
-
-
ns
CDTIO Setup Time
tCDS
40
-
-
ns
CDTIO Hold Time
tCDH
40
-
-
ns
CSN “H” Time
tCSW
150
-
-
ns
CSN Edge to CCLK “↑” (Note 27)
tCSS
50
-
-
ns
CCLK “↑” to CSN Edge (Note 27)
tCSH
50
-
-
ns
CCLK “↓” to CDTIO (at Read Command)
tDCD
-
-
70
ns
CSN “↑” to CDTIO (Hi-Z) (at Read Command)(Note 29) tCCZ
-
-
70
ns
Control Interface Timing (I2C Bus Mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
fSCL
-
tBUF
1.3
-
400
kHz
-
-
μs
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
-
-
μs
Clock Low Time
tLOW
1.3
-
-
μs
Clock High Time
tHIGH
0.6
-
-
μs
Setup Time for Repeated Start Condition
tSU:STA 0.6
-
-
μs
SDA Hold Time from SCL Falling (Note 30)
tHD:DAT
0
-
-
μs
SDA Setup Time from SCL Rising
tSU:DAT 0.1
-
-
μs
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3
μs
Setup Time for Stop Condition
tSU:STO 0.6
-
-
μs
Capacitive Load on Bus
Cb
-
-
400
pF
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
-
50
ns
Note 26. BICK rising edge must not occur at the same time as LRCK edge.
Note 27. CCLK rising edge must not occur at the same time as CSN edge.
Note 28. I2C-bus is a trademark of NXP B.V.
Note 29. It is the time of 10% potential change of the CDTIO pin when RL=1kΩ (pull-up or TVDD).
Note 30. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
MS1320-E-00
- 16 -
2011/10
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