AK4950 Datasheet, PDF (38/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
2. Interface
The input data channel of the DMDAT pin is set by DCLKP bit. When DCLKP bit = “1”, L channel data is input to the
decimation filter if DMCLK = “H”, and R channel data is input if DMCLK = “L”. When DCLKP bit = “0”, R channel data
is input to the decimation filter if DMCLK = “H”, and L channel data is input if DMCLK = “L”. The DMCLK only
supports 64fs. It outputs “L” when DCLKE bit = “0”, and outputs 64fs when DCLKE bit = “1”. In this case, necessary
clocks must be supplied to the AK4950 for ADC operation. The output data through “the Decimation and Digital Filters”
is 24bit full scale when the 1bit data density is 0%~100%.
DCLKP bit
DMCLK = “H”
DMCLK = “L”
0
Rch
Lch
(default)
1
Lch
Rch
Table 24. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)
DMCLK(64fs)
DMDAT (Lch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 30. Data In/Output Timing with Digital MIC (DCLKP bit = “1”)
DMCLK(64fs)
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 31. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)
MS1320-E-00
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2011/10