AK4950 Datasheet, PDF (59/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
[Stereo Line Output Control Sequence (in case of using a Pop Noise Reduction Circuit)]
(2)
PMLO bit
(1)
(3)
LOPS bit
(5)
(4)
(6)
LOUT, ROUT pins
≥ 300 ms
Normal Output
≥ 300 ms
99%
Common Voltage
1%
Common Voltage
Figure 43. Stereo Line Output Control Sequence (in case of using a Pop Noise Reduction Circuit)
(1) Set LOPS bit = “1”. Stereo line output enters the power-save mode.
(2) Set PMLO bit = “1”. Stereo line output exits the power-down mode.
LOUT and ROUT pins rise up to common voltage. Rise time is 200ms (max 300ms) when C=1μF.
(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits the power-save mode.
Stereo line output is enabled.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMLO bit = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to 1% of the common voltage. Fall time is 200ms (max 300ms) at C=1μF.
(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits the power-save mode.
< Mono Mixing Output >
Mono mixing outputs are available by setting MONO1-0 bits. Input data from the SDTI pin can be converted to mono
signal [(L+R)/2] and are output via LOUT and ROUT pins. (Figure 32)
MONO1 bit
0
0
1
1
MONO0 bit
LOUT pin
ROUT pin
0
Lch
Rch
1
Lch
Lch
0
Rch
Rch
1
(Lch+Rch)/2
(Lch+Rch)/2
Table 44. LOUT/ROUT pin Output Data Switch
(default)
MS1320-E-00
- 59 -
2011/10