AK4950 Datasheet, PDF (53/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
5. Example of registers set-up sequence of ALC Operation
The following registers must not be changed during ALC operation. These bits must be changed after ALC operation is
finished by ALC bit= “0”. The volume is changed in soft transition until the AK4950 becomes manual mode after ALC bit
is set to “0”.
LMTH1-0, WTM1-0, RGAIN 2-0, IREF7-0, OREF7-0, RFST1-0 bits
Manual Mode
Example:
Recovery Wait Time = 21.3ms@48kHz
Recovery Quantity = 0.0005 dB
Fast Recovery Quantity = 0.0032 dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
WR ( IVL/R 7-0)
(1) Addr=20H&21H Data=E1H
WR (IREF7-0)
* The value of IVOL should be
the same or smaller than REF’s
(2) Addr=24H, Data=E1H
WR (WTM 1-0, RFST1-0)
(3) Addr=26H, Data=30H
WR (RGAIN2-0, LMTH1-0; ALC = “1”)
(4) Addr=27H, Data=59H
ALC Operation
Figure 39. Registers Set-up Sequence at ALC1 Operation (recording path)
MS1320-E-00
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2011/10