AK4950 Datasheet, PDF (31/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
■ System Reset
Upon power-up, the AK4950 must be reset by bringing the PDN pin = “L”. It ensures that all internal registers are
initialized. When restart the AK4950 after powered-down, the PDN pin should be set to “L” and hold 10ms. Then set the
PDN pin to “H”, and INIT bit should be set to “1” after clocks are input. It is recommended to set the PDN pin = “L”
before power up the AK4950.
The ADC starts an initialization cycle if the one of PMADL or PMADR bit is set to “1” when both of the PMADL and
PMADR bits are “0”. The initialization cycle is set by ADRST bit (Table 16). During the initialization cycle, the ADC
digital data outputs of both channels are forced to “0” in 2's complement. The ADC output reflects the analog input signal
after the initialization cycle is finished. When using a digital microphone, the initialization cycle is the same as ADC’s.
(Note) The initial data of ADC has offset data that depends on microphones and the cut-off frequency of HPF. If this
offset is not small, make initialization cycle longer by setting ADRST bit or do not use the first data of ADC
outputs.
ADRST bit
0
1
Init Cycle
Cycle
fs = 8kHz
fs = 16kHz
1059/fs
132.4ms
66.2ms
267/fs
33.4ms
16.7ms
Table 16. ADC Initialization Cycle
fs = 44.1kHz
24ms
6.1ms
■ Audio Interface Format
Four types of data formats are available and selected by setting the DIF1-0 bits (Table 17). In all modes, the serial data is
MSB first, 2’s complement format. Audio interface formats are supported in both master and slave modes. LRCK and
BICK are output from the AK4950 in master mode, but must be input to the AK4950 in slave mode. The SDTO is clocked
out on the falling edge (“↓”) of BICK and the SDTI is latched on the rising edge (“↑”) of BICK.
Mode
0
1
2
3
DIF1 bit
0
0
1
1
DIF0 bit
0
1
0
1
SDTO (ADC)
24bit MSB justified
24bit MSB justified
24bit MSB justified
I²S Compatible
SDTI (DAC)
24bit LSB justified
16bit LSB justified
24bit MSB justified
I²S Compatible
Table 17. Audio Interface Format
BICK
≥ 48fs
≥ 32fs
≥ 48fs
=32fs or
≥ 48fs
Figure
Figure 23
Figure 24
Figure 25
(default)
Figure 26
MS1320-E-00
- 31 -
2011/10