AK4950 Datasheet, PDF (102/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
■ Stop of Clock
Master clock can be stopped when ADC, DAC, Digital MIC and Programmable Filter are not in operation.
1. PLL Master Mode
PMPLL bit
(Addr:01H, D16)
MCKO bit
(Addr:01H, D17)
External MCKI
"0" or "1"
Input
(1)
(2)
(3)
Example:
Audio I/F Format: MSB justified (ADC & DAC )
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode
(1) (2) Addr:01H, Data:08H
(3) Stop an external MCKI
Figure 76. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop the external master clock.
2. PLL Slave Mode (BICK pin)
PMPLL bit
(Addr:01H, D016
External BICK
External LRCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 77. Clock Stopping Sequence (2)
<Example>
(1) Power down of the PLL: PMPLL bit = “1” → “0”
(2) Stop the external master clock.
MS1320-E-00
- 102 -
2011/10