AK4950 Datasheet, PDF (68/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
■ Serial Control Interface
(1) 3-wire Mode
Internal registers may be written by using 3-wire mode interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control or Output data (MSB first, 24bits).
Address and data is clocked in on the rising edge of CCLK and data is clocked out on the falling edge.
Data writings become available on the rising edge of CSN. When reading the data, the CDTIO pin changes to output
mode at the falling edge of 8th CCLK and outputs data in D23-D0. However this reading function is available only when
READ bit = “1”. When READ bit = “0”, the CDTIO pin stays as Hi-Z even after the falling edge of 8th CCLK. The data
output finishes on the rising edge of CSN. The CDTIO is placed in a Hi-Z state except when outputting the data at read
operation mode. Clock speed of CCLK is 5MHz (max). The value of internal registers are initialized by the PDN pin =
“L”.
The registers on the address after 20H are for CRAM of the DSP. Writing data is automatically stored in CRAM when
COEW bit is “1” (Figure 53). In this case, PMPFIL bit should be set to “0”. Read commands are not valid.
Note 41. Data reading is only available on the following addresses; 00 ~ 0FH and 20H ~ 2FH. When reading the other
addresses, the register values are invalid.
(1)-1. When accessing to the address 00H ~ 2FH (COEW bit = “0”)
CSN
CCLK _{“H” or “L”}
0 _{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
CDTI “H” or “L”
H A6 A5 A4 A3 A2 A1 A0 D23 D22 D21 D20 D19 D18 D17 D16
CSN
CCLK
CDTI
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
“H” or “L”
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
“H” or “L”
A6-A0: Register Address
D23-D0: Control data (Input) at Write Command (Write only)
Figure 52. 3-wire Mode Control Interface Timing (COEW bit = “0”)
MS1320-E-00
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2011/10