AK4950 Datasheet, PDF (70/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4950 supports the fast-mode I²C-bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins must be
connected to (TVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 54 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 62). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant six bits of the slave address are fixed as “001001”. The next bit is CAD0 (device address bit).
This bit identifies the specific device on the bus. The hard-wired input pin (CAD0 pin) sets these device address bits
(Figure 56). If the slave address matches that of the AK4950, the AK4950 generates an acknowledge and the operation is
executed. The master must generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the
acknowledge clock pulse (Figure 63). A R/W bit value of “1” indicates that the read operation is to be executed, and “0”
indicates that the write operation is to be executed.
The second byte consists of the control register address of the AK4950 and the format is MSB first. (Figure 57). The data
after the second byte contains control data. The format is MSB first, 8bits (Figure 58). The AK4950 generates an
acknowledge after each byte is received. Data transfer is always terminated by a STOP condition generated by the master.
A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 62).
The AK4950 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4950
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 2FH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of the data line
can only be changed when the clock signal on the SCL line is LOW (Figure 64) except for the START and STOP
conditions.
The data length is different (8bit or 24bit) depending on the data address.
Address
Data length
00H ~ 2FH
8bit
80H ~ FFH
24bit
Table 55. Data Length in I²C-bus Mode
S
T
S
A
R/W="0"
T
R
O
T
P
SDA
Slave
S _Address
Sub
Address(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 54. Data Transfer Sequence at I²C Bus Mode (00H ~ 2FH)
MS1320-E-00
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2011/10