AK4950 Datasheet, PDF (93/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
2. When the external clock (BICK pin) is used in PLL Slave mode.
Power Supply
PDN pin
PLL3-0 bits
(Addr:07H, D20-23)
FS3-0 bits
(Addr:08H, D19-16)
PMPLL bit
(Addr:01H, D16)
BICK pin
LRCK pin
Internal Clock
INIT bit
(Addr:0EH, D16)
(1)
(2)
1msec(min)
(3)
Default
(4)
Default
"0011"
"10xx"
Input
(5)
(6)
(7)
Example:
Audio I/F Format : MSB justified (ADC & DAC )
PLL R eference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 48kHz
4f₍s₁₎of_{Power Supply & PDN pin = “L” Æ “H”}
(2) Wait time (min)1ms
(3) Addr:07H, Data:32H
(4) Addr:08H, Data:08H
(5) Addr:01H, Data:01H
Figure 67. Clock Set Up Sequence (2)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time (1) of 150ns or more is needed to reset the AK4950.
(2) PDN pin reset release waiting time
Wait time of 1ms or more is needed for the internal VCOM voltage rising.
(3) PLL mode setting. (When the reference clock is BICK = 64fs, PLL3-0 bits = “0011”)
(4) Sampling frequency setting. (In case of fs = 48kHz, FS3-0 bits = “10xx”)
(5) PLL lock time is 2ms (max) after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK pin)
is supplied.
(6) Normal operation starts after the PLL is locked.
(7) Digital Function Initializing
Digital functions can be initialized by setting INIT bit = “0” → “1” after normal clock is output. The initializing
time is 1/512fs x 18,000 [s]. INIT bit returns to “0” automatically when the initialization is finished. This
initialization must be executed when using ALC and Programmable Filter.
MS1320-E-00
- 93 -
2011/10