AK4950 Datasheet, PDF (96/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
■ MIC Input Recording (Stereo)
PMMP bit
ADRST bit
XXH
(Addr:01H, D18, D23)
(1)
MIC Control _{X, XXX}
(Addr:02H, D19-16)
(2)
0FH
0110
IVL7-0 bits
(Addr:20H)
ALC Control 1
(Addr:24H )
ALC Control 2
(Addr:26H)
ALC Control 3
(Addr:27H)
Digital Filter Path
(Addr:2CH)
Filter Select1
(Addr:2DH)
XXH
XXH
(3)
(4)
XXH
(5)
XXH
(6)
XXH
(7)
XXH
COEW bit
(Addr:0DH, D16)
Filter Co-ef
(Addr:03H,04H,06H
Control Data MSB = 'L')
0
XXH
(8)
(9)
(10)
E1H
E1H
30H
59H
17H
10H
1
0FD82DH (Addr: 03H)
FD27D4H (Addr : 04H)
0FB05BH (Addr : 06H)
19H
(13)
ALC State
ALC Disable
ALC Enable
ALC Disable
PMPFIL bit
PMADL/R bit
(Addr:00H, D16, D17, D23
Control Data MSB = 'H')
(11) _1059/fs
(12)
SDTO pin
State
0 data Output
Normal
Initialize _{Data Output} 0 data output
Example:
Control I/F = 3-wire
PLL Master Mode (MCKO output)
Audio I/F Format: MSB justified
Pre MIC Amp: +18dB
MIC Power ON
Sampling Frequency: 48kHz
ALC setting:Refer to Table 34
HPF2: fc=150Hz, ADRST bit = “0”
(1) Addr:01H, Data:0FH
(2) Addr:02H, Data:06H
(3) Addr:20H, Data:E1H
(4) Addr:24H, Data:E1H
(5) Addr:26H, Data:30H
(6) Addr:27H, Data:59H
(7) Addr:2CH, Data:17H
(8) Addr:26H, Data:03H
(9) Addr:0DH, Data:01H
(10) Addr:03H, Data:0FD82DH
Addr:04H, Data:FD27D4H
Addr:06H , Data:0FB05BH
(11) Addr:00H, Data:83H
Recording
(12) Addr:00H, Data:00H
(13) Addr:27H, Data:19H
Figure 70. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC1 setting at fs=48kHz. If the parameter of the ALC1 is changed, please refer to
the Figure 39. At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Power Up MIC Power: PMMP bit = “0” → “1”, ADRST bit (initializing cycle) setting (Addr = 01H)
(2) Set up gain for microphone by MGAIN3-0 bits (Addr = 02H)
(3) Set up ALC starting IVOL value. (Addr = 20H)
(4) Set up IREF value. (Addr = 24H)
(5) Set up RFST1-0 and WTM1-0 bits for ALC (Addr= 26H)
(6) Set up LMTH1-0, RGAIN2-0 bits and ALC bit. (Addr=27H)
(7) Set up Programmable Filter Path: PFSDO bit = ADCPF bit = “1” (Addr=2CH)
(8) Switch ON/OFF of the Programmable Filter: HPF bit = “1” (Addr= 2DH)
(9) Set up COEW bit = “1” (Addr = 0DH)
When COEW bit = “1”, registers on the register map 1 and 2 can be accessed. Set the most significant bit
(MSB) of the control data to “1” (Figure 52) to access registers on the register map 1, and set “0” to access
registers on the register map 2 (Figure 53).
(10) Set up Coefficient of the Programmable Filter (Addr=03H, 04H, 06H: Control data MDB = “L”)
(11) Power up of the ADC and Programmable Filter: (PMADL=PMADR=PMPFIL bits = “0” → “1”)
The initialization cycle of the ADC is 1059/fs=22.06ms@fs=48kHz when ADRST bit = “0”. ADC outputs “0”
during the initialization. ALC starts operation at the value set by IVOL (3).
(12) Power down of the microphone, ADC and Programmable Filter: (PMADL=PMADR=PMPFIL bits = “1” →
“0”)
(13) ALC Disable: ALC bit “1” → “0”
MS1320-E-00
- 96 -
2011/10