AK4950 Datasheet, PDF (103/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP

[AK4950]
3. PLL Slave Mode (MCKI pin)
PMPLL bit
(Addr:01H, D16)
MCKO bit
(Addr:01H, D17)
External MCKI
(1)
(1)
(2)
Input
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 78. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop the MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
4. External Clock Mode
External MCKI
External BICK
External LRCK
Input
Input
Input
(1)
Example
(1)
Audio I/F Format :MSB justified(ADC & DAC)
Input MCKI frequency:1024fs
(1)
(1) Stop the external clocks
Figure 79. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
■ Power Down
Power supply current can be shut down (typ. 1μA) by stopping clocks and setting PDN pin = “L”. When the PDN pin =
“L”, the registers are initialized.
MS1320-E-00
- 103 -
2011/10