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AK4950 Datasheet, PDF (44/106 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/SPK/Cap-less VIDEO-AMP & mini DSP
[AK4950]
(4) Gain Compensation (EQ0)
Gain compensation is used to compensate the frequency response and the gain that is changed by the stereo separation
emphasis filter. Gain compensation is composed of the Equalizer (EQ0) and the Gain (0dB/+6dB/+12dB/+24dB).
Address 19H ~ 1DH(3-wire mode, COEW bit = “1”) and address 99H~9DH (I2C mode) set the coefficient of EQ0.
GN1-0 bits set the gain (Table 26). EQ0 bit controls ON/OFF of EQ0. When EQ is OFF and the gain is 0dB, the audio
data passes this block by 0dB gain. The coefficient should be set when EQ0 bit = “0” or PMPFIL bit = “0”. The EQ0 starts
operation 2/fs(max) after when EQ0 bit =PMPFIL bit= “1” is set.
1) When EQ0 = High boost Filter
fs: Sampling Frequency
fc: Cutoff Frequency
β = A/Q
A = boost gain. Example) Boost gain = +12dB (A = 10 Gain [dB] / 40 ) when A=2.
Gain =20 log (Q)[dB] for fs. Normally Q should be set to 0.7071.
Register Setting (Register Map 2) (Note 37)
1
A0: Register Addr = 19H(3-wire mode), 99H(I2C mode)
A1: Register Addr = 1AH(3-wire mode), 9AH(I2C mode)
A2: Register Addr = 1BH(3-wire mode), 9BH(I2C mode)
B1: Register Addr = 1CH(3-wire mode), 9CH(I2C mode)
B2: Register Addr = 1DH(3-wire mode), 9DH(I2C mode)
A0 =
A × ((A+1) + (A–1) × cos (2πfc/fs) + β × sin (2πfc/fs))
(A+1) – (A–1) × cos (2πfc/fs) + β × sin (2πfc/fs)
A1 =
–2A × ((A–1) + (A+1) × cos (2πfc/fs))
(A+1) – (A–1) × cos (2πfc/fs) + β × sin (2πfc/fs)
A2 =
A × ((A+1) – (A–1) × cos (2πfc/fs) – β × sin (2πfc/fs))
(A+1) – (A–1) × cos (2πfc/fs) + β × sin (2πfc/fs)
B1 =
–2 × ((A–1) – (A+1) × cos (2πfc/fs))
(A+1) – (A–1) × cos (2πfc/fs) + β × sin (2πfc/fs)
B2 =
–
(A+1) + (A–1) × cos (2πfc/fs) – β × sin (2πfc/fs))
(A+1) – (A–1) × cos (2πfc/fs) + β × sin (2πfc/fs)
Transfer Function
Hx (z) =
A0 + A1 z −1 + A2z −2
1 − B1z −1− B2z −2
The cut-off frequency must be set as below.
fc1 / fs < 0.497
Gain
MS1320-E-00
fc
Frequency
Figure 37. EQ0 Frequency Response (High –boost)
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