AK4953A Datasheet, PDF (93/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
3. PLL Slave (MCKI pin)
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
(1)
(1)
(2)
Input
Example
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: MCKI
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 65. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
4. EXT Slave Mode
External MCKI
External BICK
External LRCK
Input
Input
Input
(1)
Example
(1)
Audio I/F Format :MSB justified(AD C & DAC)
Input MCKI frequency:256fs
(1)
(1) Stop the external clocks
Figure 66. Clock Stopping Sequence (4)
<Example>
(1) Stop the external MCKI, BICK and LRCK clocks.
■ Power down
Power supply current can not be shut down by stopping clocks and setting PMVCM bit = “0”. Power supply current can
be shut down (typ. 1μA) by stopping clocks and setting the PDN pin = “L”. When the PDN pin = “L”, all registers are
initialized.
MS1252-E-00
- 93 -
2010/10