AK4953A Datasheet, PDF (80/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
CONTROL SEQUENCE
■ Clock Set up
When any circuits of the AK4953A are powered-up, the clocks must be supplied.
1. PLL Master Mode
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
MCKI pin
M/S bit
(Addr:01H, D3)
BICK pin
LRCK pin
MCKO pin
(1)
(2) (3)
(4)
> 3ms
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
(5)
Input
10msec(max)
(6)
10msec(max)
(8)
(7)
Output
(9)
Output
(2)Dummy command
Addr:01H, Data:08H
Addr:05H, Data:4AH
Addr:06H, Data:0DH
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:0BH
MCKO, BICK and LRCK output
Figure 51. Clock Set Up Sequence (1)
<Example>
(1) After Power Up, PDN pin “L” → “H”.
“L” time of 150ns or more is needed to reset the AK4953A.
(2) After Dummy Command input, M/S, DIF1-0, BCKO, PLL3-0, FS3-0, DS and PS1-0 bits must be set during
this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time is 3ms (max).
(4) In case of using MCKO output: MCKO bit = “1”
In case of not using MCKO output: MCKO bit = “0”
(5) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source, and PLL
lock time is 10ms (max).
(6) BICK pin outputs “H” and LRCK pin outputs “L” during this period.
(7) The AK4953A starts to output the LRCK and BICK clocks after the PLL became stable. Then normal operation
starts.
(8) The invalid frequency is output from the MCKO pin during this period if MCKO bit = “1”.
(9) The normal clock is output from the MCKO pin after the PLL is locked if MCKO bit = “1”.
MS1252-E-00
- 80 -
2010/10