AK4953A Datasheet, PDF (90/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
■ Speaker-Amp Output
FS3-0 bits
(Addr:06H, D3-0)
DACS bit
(Addr:02H, D5)
0000
(1)
(2)
1101
SPKG1-0 bits
(Addr:03H, D7-6)
Timer Select
(Addr:0AH)
00
00H
ALC Control 3
(Addr:0DH)
28H
ALC Control 1
(Addr:0BH)
00H
OVL/R7-0 bits
(Addr:11H&12H)
91H
Digital Filter Path _03H
(Addr:1DH)
(3)
(4)
(5)
(6)
(7)
(8)
01
70H
28H
C1H
91H
04H
ALC2 State
ALC2 Disable
ALC2 Enable
PMPFIL bit
PMDAC bit
(Addr:00H,D7&D2)
PMSPK bit
(Addr:00H, D4)
SPPSN bit
(Addr:02H, D7)
SPP pin
(9)
Hi-Z
> 1 ms
(10)
(11)
Normal Output
(12)
ALC2 Disable
(13)
Hi-Z
SPN pin
Hi-Z
SVDD/2 Normal Output SVDD/2 Hi-Z
Figure 61. Speaker-Amp Output Sequence
Example:
PLL Master Mode
Audio I/F Format: MSB justified
Sampling Frequency:44.1KHz
Digital Volume: 0dB
ALC2: Enable
Programmable Filter OFF
(1) Addr:06H, Data:0DH
(2) Addr:02H, Data:23H
(3) Addr:03H, Data:40H
(4) Addr:0AH, Data:70H
(5) Addr:0DH, Data:28H
(6) Addr:0BH, Data:C1H
(7) Addr:11H & 12H, Data:91H
(8) Addr:1DH, Data:04H
(9) Addr:00H, Data:D4H
(10) Addr:02H, Data:A3H
Playback
(11) Addr:02H, Data:23H
(12) Addr:02H, Data:03H
(13) Addr:00H, Data:40H
<Example>
At first, clocks must be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4953A is PLL mode, DAC and Speaker-Amp of (9)
must be powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of DAC → SPK-Amp: DACS bit = “0” → “1”
(3) SPK-Amp gain setting: SPKG1-0 bits = “00” → “01”
(4) Set up Timer Select for ALC2 (Addr = 0AH)
(5) Set up OREF value for ALC2 and RGAIN1-0 bits (Addr = 0DH)
(6) Set up LMTH1-0, LMAT1-0, ZELMIN, ALC2 and LFST bits (Addr = 0BH)
(7) Set up the output digital volume (Addr = 11H, 12H)
Set up OVOL value at ALC2 operation start. When OVOLC bit is “1” (default), OVL7-0 bits set the volume of
both channels. After DAC is powered-up, the digital volume changes from default value (0dB) to the register
setting value by the soft transition. When ALC2 bit = “0”, it could be digital volume control.
(8) Set up Programmable Filter Path: PFDAC, ADCPF, PFSDO bits (Addr = 1DH)
(9) Power up DAC, Programmable Filter and Speaker: PMDAC = PMPFIL = PMSPK bits = “0” → “1”
(10) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
(11) Enter Speaker-Amp Power-save-mode: SPPSN bit = “1” → “0”
(12) Disable the path of “DAC → SPK-Amp”: DACS bit = “1” → “0”
(13) Power down DAC, Programmable Filter and Speaker: PMDAC = PMPFIL = PMSPK bits = “1” → “0”
MS1252-E-00
- 90 -
2010/10