AK4953A Datasheet, PDF (87/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
■ Headphone-Amp Output
FS3-0 bits
(Addr:06H, D3-0)
0000
(1)
1101
DVL7-0 bits
(Addr:13H)
18H
(2)
18H
Digital Filter Path
03H
03H
(Addr:1DH)
(3)
PMDAC bit
(Addr:00H, D2)
(4)
(5)
PMHPL/R bits
(Addr:01H, D5-4)
> 35ms
HPL pin
HPR pin
Figure 58. Headphone-Amp Output Sequence
Example:
PLL, Master Mode
Audio I/F Format: MSB justified
Sampling Frequency: 44.1KHz
Digital Volume 2: 0dB
PMBP bit = “0”
Programmable Filter OFF
(1) Addr:06H, Data:0DH
(2) Addr:13H, Data:18H
(3) Addr:1DH, Data:03H
(4) Addr:00H, Data:44H
Addr:01H, Data:39H
Playback
(5) Addr:01H, Data:09H
Addr:00H, Data:40H
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4953A is PLL mode, DAC of (4) must be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the output digital volume 2 (Addr = 13H)
(3) Set up Programmable Filter Path: PFDAC, ADCPF, PFSDO bits (Addr = 1DH)
(4) Power up DAC and Headphone-Amp: PMDAC = PMHPL = PMHPR bits = “0” Æ “1”
When PMHPL = PMHPR bits = “1”, the charge pump circuit starts to power-up. The power-up time of
Headphone-Amp block is 35ms (max).
(5) Power down DAC and Headphone-Amp: PMDAC = PMHPL = PMHPR bits = “1” Æ “0”
MS1252-E-00
- 87 -
2010/10