AK4953A Datasheet, PDF (27/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the internal PLL
circuit generates MCKO, BICK and LRCK clocks. The MCKO output frequency is selected by PS1-0 bits (Table 10) and
the output is enabled by MCKO bit. The BICK output frequency is selected between 32fs or 64fs, by BCKO bit (Table
11).
AK4953A
11.2896MHz,12MHz, 13.5MHz,
24MHz, 27MHz
DSP or μP
MCKI
MCKO
B IC K
LRCK
SDTO
SDTI
256fs/128fs/64fs/32fs
32fs, 64fs
1f s
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 14. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 10. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BCKO bit BICK Output Frequency
0
32fs
(default)
1
64fs
Table 11. BICK Output Frequency at Master Mode
MS1252-E-00
- 27 -
2010/10