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| AK4953A Datasheet, PDF (26/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP | |||
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[AK4953A]
â PLL Unlock State
1) PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
In this mode, the LRCK pin goes to âLâ and the BICK pin goes to âHâ, and irregular frequency clock is output from the
MCKO pin when MCKO bit is â1â before the PLL goes to lock state after PMPLL bit = â0â Ã â1â. If MCKO bit is â0â,
the MCKO pin outputs âLâ (Table 8).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to normal state
after a period of 1/fs.
PLL State
MCKO pin
BICK pin
MCKO bit = â0â MCKO bit = â1â
LRCK pin
After PMPLL bit â0â â â1â
âLâ Output
Invalid
âHâ Output
âLâ Output
PLL Unlock (except the case above) âLâ Output
Invalid
Invalid
Invalid
PLL Lock
âLâ Output
Table 10
Table 11
1fs Output
Table 8. Clock Operation at PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
2) PLL Slave Mode (PMPLL bit = â1â, M/S bit = â0â)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = â0â â
â1â. Then, the clock selected by Table 10 is output from the MCKO pin when PLL is locked. ADC and DAC output
invalid data when the PLL is unlocked. DAC should be powered up by PMDAC bit â0â â â1â after PLL is locked.
PLL State
MCKO pin
MCKO bit = â0â MCKO bit = â1â
After PMPLL bit â0â â â1â
âLâ Output
Invalid
PLL Unlock (except the case above) âLâ Output
Invalid
PLL Lock
âLâ Output
Table 10
Table 9. Clock Operation at PLL Slave Mode (PMPLL bit = â1â, M/S bit = â0â)
MS1252-E-00
- 26 -
2010/10
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