AK4953A Datasheet, PDF (46/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
Register Name
LMTH1-0
ZELMN
ZTM1-0
WTM2-0
OREF5-0
OVL7-0,
OVR7-0
LMAT1-0
LFST
RGAIN1-0
RFST1-0
ALC2
Comment
fs=8kHz
Data
Operation
Limiter detection Level
01
−4.1dBFS
Limiter zero crossing detection
0
Enable
Zero crossing timeout period
01
32ms
Recovery waiting period
*WTM2-0 bits must be the same value 001
32ms
or larger value than ZTM1-0 bits
Maximum gain at recovery operation 28H
+6dB
Gain of VOL
91H
0dB
Limiter ATT step
00
1 step
Fast Limiter Operation
1
ON
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 37. Example of the ALC Setting (Playback)
fs=44.1kHz
Data
Operation
01
−4.1dBFS
0
Enable
11
23.2ms
100
46.4ms
28H
+6dB
91H
0dB
00
1 step
1
ON
00
1 step
00
4 times
1
Enable
5. Example of registers set-up sequence of ALC Operation
The following registers must not be changed during ALC operation. These bits must be changed after ALC operation is
finished by ALC1 bit=ALC2 bit = “0”. All ALC outputs are “0” until manual mode starts when ALC1 bit =ALC2 bit =
“0”.
LMTH1-0, LMAT1-0, ZTM1-0, WTM2-0, RGAIN 1-0, IREF7-0, ZELMN, RFST1-0, LFST bits
Manual Mode
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC1 bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=0AH, Data=24H
WR (IREF7-0)
(2) Addr=0CH, Data=E1H
WR (IVL/R7-0) ^{* The value of IVOL should be}
the same or smaller than REF’s
WR (RGAIN1-0)
(3) Addr=0FH&10H, Data=E1H
(4) Addr=0DH, Data=28H
WR (LFST, ZELMN, LMAT1-0, LMTH1-0; ALC1= “1”)
(5) Addr=0BH, Data=A1H
ALC Operation
[Note] WR: Write
Figure 35. Registers Set-up Sequence at ALC1 Operation (recording path)
MS1252-E-00
- 46 -
2010/10