AK4953A Datasheet, PDF (25/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) circuit generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock times, when the AK4953A is supplied stable clocks or the sampling frequency is
changed after PLL is powered-up (PMPLL bit = “0” → “1”), are shown in Table 5.
1) PLL Mode Setting
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
PLL Lock Time
(max)
2
0
0
1
0
BICK pin
32fs
2 ms
3
0
0
1
1
BICK pin
64fs
2 ms
4
0
1
0
0
MCKI pin
11.2896MHz
10 ms
6
0
1
1
0
MCKI pin
12MHz
10 ms
7
0
1
1
1
MCKI pin
24MHz
10 ms
12
1
1
0
0
MCKI pin
13.5MHz
10 ms
13
1
1
0
1
MCKI pin
27MHz
10 ms
Others
Others
N/A
Note 41. PLL3-0 bits = “0000”(Default: N/A). When PLL mode is used, PLL3-0 bits must be set before PMPLL bit = “0”
Æ “1”.
Table 5. PLL Mode Setting (*fs: Sampling Frequency, N/A: Not Available)
2) Setting of sampling frequency in PLL Mode
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 6.
Mode FS3 bit FS2 bit FS1 bit FS0 bit DS bit Sampling Frequency
0
0
0
0
0
8kHz
(default)
1
0
0
0
1
12kHz
2
0
0
1
0
16kHz
3
0
0
1
1
24kHz
4
0
1
0
0
0
7.35kHz
5
0
1
0
1
11.025kHz
6
0
1
1
0
14.7kHz
7
0
1
1
1
22.05kHz
8
1
0
0
0
32kHz
9
1
0
0
1
48kHz
10
1
0
1
0
1
11
1
0
1
1
64kHz
96kHz
12
13
1
1
1
1
0
0
0
1
0
29.4kHz
44.1kHz
15
1
1
1
1
1
88.2kHz
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1”
(Reference Clock = MCKI pin), (N/A: Not Available)
When PLL2 bit is “0” (PLL reference clock input is BICK pin), the sampling frequency is selected by FS1-0 bits (Table
7).
Mode
FS3 bit
FS2 bit
FS1 bit FS0 bit DS bit
Sampling Frequency
Range
0
x
x
0
0
7.35kHz ≤ fs ≤ 12kHz (default)
1
x
x
0
1
0
12kHz < fs ≤ 24kHz
2
x
x
1
0
24kHz < fs ≤ 48kHz
3
x
x
1
1
1
48kHz < fs ≤ 96kHz
Others
Others
N/A
Table 7. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
(PLL Reference Clock: BICK pin), (x: Don’t care, N/A: Not Available)
MS1252-E-00
- 25 -
2010/10