AK4953A Datasheet, PDF (28/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pins. The required clock for
the AK4953A is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5).
a) PLL reference clock: MCKI pin
The BICK and LRCK inputs must be synchronized with MCKO output. The phase between MCKO and LRCK is not
important. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 10) and the output is enabled by MCKO
bit. Sampling frequency can be selected by FS3-0 bits and DS bit. (Table 6)
AK4953A
MCKI
MCKO
B IC K
LRCK
SDTO
SDTI
11.2896MHz, 12MHz, 13.5MHz,
24MHz, 27MHz
DSP or μP
256fs /128fs/64fs/32fs
≥ 32fs
1f s
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 15. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
b) PLL reference clock: BICK pin
The sampling frequency corresponds to a range from 7.35kHz to 96kHz by changing FS3-0 bits and DS bit (Table 7).
AK4953A
MCKO
MCKI
B IC K
LRCK
SDTO
SDTI
DSP or μP
32fs or 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 16. PLL Slave Mode 2 (PLL Reference Clock: BICK pin)
MS1252-E-00
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2010/10