AK4953A Datasheet, PDF (81/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
2. PLL Slave Mode (BICK pin)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D0)
BICK pin
(1)
(2) (3)
> 3ms
Internal Clock
Example:
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
4f₍s₁o₎ f_{Power Supply & PDN pin = “L” Æ “H”}
(2) Dummy command
Addr:05H, Data:32H
Addr:06H, Data:02H
Input
(4)
(3) Addr:00H, Data:40H
(5)
Figure 52. Clock Set Up Sequence (2)
(4) Addr:01H, Data:01H
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4953A.
(2) After Dummy Command input, DIF1-0, PLL3-0, FS3-0 and DS bits must be set during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time is 3ms (max).
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK pin) is supplied. PLL
lock time is 2ms (max) when BICK is a PLL reference clock.
(5) Normal operation stats after that the PLL is locked.
MS1252-E-00
- 81 -
2010/10