AK4953A Datasheet, PDF (37/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
2. Interface
The input data channel of the DMDAT pin is set by DCLKP bit. When DCLKP bit = “1, Lch data is input to the
decimation filter if DMCLK = “H”, and Rch data is input if DMCLK = “L”. When DCLKP bit = “0”, Rch data is input to
the decimation filter if DMCLK = “H”, and Lch data is input if DMCLK = “L”. The DMCLK pin outputs “L” when
DCLKE bit = “0”, and only supports 64fs. In this case, necessary clocks must be supplied to the AK4953A for ADC
operation. The output data through “the Decimation and Digital Filters” is 24bit full scale when the 1bit data density is
0%~100%.
DCLKP bit
DMCLK = “H”
DMCLK = “L”
0
Rch
Lch
1
Lch
Rch
Table 24. Data In/Output Timing with Digital MIC
(default)
DMCLK(64fs)
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 28. Data In/Output Timing with Digital MIC (DCLKP bit = “1”)
DMCLK(64fs)
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 29. Data In/Output Timing with Digital MIC (DCLKP bit = “0”)
MS1252-E-00
- 37 -
2010/10