AK4953A Datasheet, PDF (31/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
■ System Reset
Upon power-up, the AK4953A must be reset by bringing the PDN pin = “L”. This reset is released when a dummy
command is input after the PDN pin = “H”. This ensures that all internal registers reset to their initial value. Dummy
command is executed by writing all “0” to the register address 00H. It is recommended to set the PDN pin = “L” before
power up the AK4953A.
CSN
CCLK _{“H” or “L”}
0 _{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
“H” or “L”
CDTIO “H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “H” or “L”
R/W: READ/WRITE (“1”: WRITE)
A6-A0: Register Address (00H)
D7-D0: Control data (Input), (00H)
Figure 19. Dummy Command in 3-wired Serial Mode
S
T
A
R/W ="0"
R
T
SDA
S
Slave
Address
Sub
Address(00H)
S
T
O
P
Data(00H)
P
N
N
N
A
A
A
C
C
C
K
K
K
Figure 20. Dummy Command in I²C-bus Mode
The ADC enters an initialization cycle when the PMADL or PMADR bit is changed from “0” to “1”. The initialization
cycle time is set by ADRST1-0 bits (Table 17). During the initialization cycle, the ADC digital data outputs of both
channels are forced to a 2's complement, “0”. The ADC output reflects the analog input signal after the initialization cycle
is complete. When using a digital microphone, the initialization cycle is the same as ADC’s.
Note 42. The initial data of ADC has offset data that depends on the condition of the microphone and the cut-off
frequency of HPF. If this offset is not small, make initialization cycle longer by setting ADRST1-0 bits or do not
use the initial data of ADC.
ADRST1
bit
0
0
1
1
ADRST0
bit
0
1
0
1
Init Cycle
Cycle fs = 8kHz fs = 16kHz fs = 44.1kHz
1059/fs 132.4ms
66.2ms
24ms
267/fs
33.4ms
16.7ms
N/A
2115/fs 264.4ms
132.2ms
48ms
2115/fs 264.4ms
132.2ms
48ms
Table 17. ADC Initialization Cycle (N/A: Not Available)
fs = 96kHz
11ms
N/A
22ms
22ms
(default)
MS1252-E-00
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2010/10