AK4953A Datasheet, PDF (70/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
Addr
08H
Register Name
Digital MIC
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0 PMDMR PMDML DCLKE
0
DCLKP DMIC
R
R
R/W
R/W
R/W
R
R/W
R/W
0
0
0
0
0
0
0
0
DMIC: Digital Microphone Connection Select
0: Analog Microphone (default)
1: Digital Microphone
DCLKP: Data Latching Edge Select
0: Lch data is latched on the DMCLK rising edge (“↑”). (default)
1: Lch data is latched on the DMCLK falling edge (“↓”).
DCLKE: DMCLK pin Output Clock Control
0: “L” Output (default)
1: 64fs Output
PMDML/R: Input Signal Select with Digital Microphone (Table 21)
Default: “00”
ADC digital block is powered-down by PMDML = PMDMR bits = “0” when selecting a digital microphone input
(DMIC bit = “1”, INL/R bits = “00”, “01” or “10”).
Addr
09H
Register Name
Timer Select
R/W
Default
D7
D6
D5
D4
D3
ADRST1 ADRST0
0
0
0
R/W
R/W
R
R
R
0
0
0
0
0
DVTM1-0: Digital Volume Soft Transition Time Setting (Table 41)
Default: “01” (1024/fs)
This is the transition time between DVL/R7-0 bits = 00H and FFH.
ADRST1-0: ADC Initialization Cycle Setting
00: 1059/fs (default)
01: 267/fs
10: 2115/fs
11: 2115/fs
D2
D1
D0
0
DVTM1 DVTM0
R
R/W
R/W
0
0
1
Addr
0AH
Register Name
ALC Timer Select
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
ZTM1 ZTM0 WTM2 WTM1 WTM0 RFST1 RFST0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
RFST1-0: ALC First recovery Speed (Table 34)
Default: “00” (4times)
WTM2-0: ALC Recovery Waiting Period (Table 30)
Default: “000” (128/fs)
A period of recovery operation when any limiter operation does not occur during ALC operation
ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (Table 29)
Default: “00” (128/fs)
In case of the μP WRITE operation or ALC recovery operation, the volume is changed at zero crossing or
timeout.
MS1252-E-00
- 70 -
2010/10