AK4953A Datasheet, PDF (29/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4953A becomes EXT mode. Master clock can be input to the internal ADC and DAC
directly from the MCKI pin without internal PLL circuit operation. This mode is compatible with I/F of a normal audio
CODEC. The external clocks required to operate this mode are MCKI (256fs, 384fs, 512fs or 1024fs), LRCK (fs) and
BICK (≥32fs). The master clock (MCKI) must be synchronized with LRCK. The phase between these clocks is not
important. The input frequency of MCKI is selected by FS3-2 bits (Table 12).
Mode FS3 bit FS2 bit FS1 bit FS0 bit DS bit
MCKI Input
Frequency
Sampling Frequency
Range
0
0
0
7.35kHz ≤ fs ≤ 12kHz (default)
1
0
0
0
1
0
2
1
0
256fs
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
3
1
1
1
48kHz < fs ≤ 96kHz
4
0
0
7.35kHz ≤ fs ≤ 12kHz
5
0
1
0
1
0
384fs
12kHz < fs ≤ 24kHz
6
1
0
24kHz < fs ≤ 48kHz
8
0
0
7.35kHz ≤ fs ≤ 12kHz
9
1
0
0
1
0
512fs
12kHz < fs ≤ 24kHz
10
1
0
24kHz < fs ≤ 48kHz
12
1
1
0
0
0
1024fs
7.35kHz ≤ fs ≤ 12kHz
Others
Others
N/A
N/A
Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”), (N/A: Not Available)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through HPL/HPR pins is shown in Table 13.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83 dB
384fs
83 dB
512fs
95 dB
1024fs
96 dB
Table 13. Relationship between MCKI and S/N of HPL/HPR pins
AK4953A
MCKO
MCKI
B IC K
LRCK
SDTO
SDTI
256fs, 384fs,
512fs or 1024fs
≥ 32fs
1fs
DSP or μP
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 17. EXT Slave Mode
MS1252-E-00
- 29 -
2010/10