AK4953A Datasheet, PDF (18/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
Parameter
Symbol min
typ
max Units
Digital Audio Interface Timing; fs = 7.35kHz ~ 48kHz, C_L=100pF
DMCLK Output Timing
Period
tSCK
-
1/(64fs)
-
ns
Rising Time
tSRise
-
-
10
ns
Falling Time
tSFall
-
-
10
ns
Duty Cycle
dSCK
40
50
60
%
Audio Interface Timing
DMDAT Setup Time
tSDS
50
-
-
ns
DMDAT Hold Time
tSDH
0
-
-
ns
Power-down & Reset Timing
PDN Pulse Width
(Note 36)
tPD
150
-
PMADL or PMADR “↑” to SDTO valid (Note 37)
-
ns
ADRST1-0 bits = “00”
tPDV
-
1059
-
1/fs
ADRST1-0 bits = “01”
tPDV
-
267
-
1/fs
ADRST1-0 bits = “10”, “11”
tPDV
-
2115
-
1/fs
Note 36. The AK4953A can be reset by the PDN pin = “L”.
Note 37. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
■ Timing Diagram
MCKI
LRCK
MCKO
1/fCLK
VIH
VIL
tCLKH
tCLKL
1/fs
tLRCKH
tLRCKL
1/fMCK
50%TVDD
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tMCKL
50%TVDD
dMCK = tMCKL x fMCK x 100
Note 38. MCKO is not available at EXT Master mode.
Figure 2. Clock Timing (PLL/EXT Master mode)
MS1252-E-00
- 18 -
2010/10