AK4953A Datasheet, PDF (82/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
3. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
MCKO bit
(Addr:01H, D1)
PMPLL bit
(Addr:01H, D0)
MCKI pin
MCKO pin
BICK pin
LRCK pin
(1)
(2) (3)
(4)
> 3ms
(5)
Input
10msec(max)
(6)
(7)
(8)
Output
Input
(1) Power Supply & PDN pin = “L” Æ “H”
(2)Dummy command
Addr:05H, Data:42H
Addr:06H, Data:0DH
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:03H
MCKO output start
BICK and LRCK input start
Figure 53. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4953A.
(2) After Dummy Command input, DIF1-0, PLL3-0, FS3-0, DS and PS1-0 bits must be set during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time is 3ms (max).
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 10ms (max).
(6) The normal clock is output from MCKO after PLL is locked.
(7) The invalid frequency is output from MCKO during this period.
(8) BICK and LRCK clocks must be synchronized with MCKO clock.
MS1252-E-00
- 82 -
2010/10