AK4953A Datasheet, PDF (30/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4953A becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock can be input to
the internal ADC and DAC directly from the MCKI pin without the internal PLL circuit operation. The external clock
required to operate the AK4953A is MCKI (256fs, 384fs, 512fs or 1024fs). The input frequency of MCKI is selected by
FS3-2 bits (Table 14).
Mode FS3 bit FS2 bit FS1 bit FS0 bit DS bit
MCKI Input
Frequency
Sampling Frequency
Range
0
0
0
7.35kHz ≤ fs ≤ 12kHz (default)
1
0
0
0
1
0
2
1
0
256fs
12kHz < fs ≤ 24kHz
24kHz < fs ≤ 48kHz
3
1
1
1
48kHz < fs ≤ 96kHz
4
0
0
7.35kHz ≤ fs ≤ 12kHz
5
0
1
0
1
0
384fs
12kHz < fs ≤ 24kHz
6
1
0
24kHz < fs ≤ 48kHz
8
0
0
7.35kHz ≤ fs ≤ 12kHz
9
1
0
0
1
0
512fs
12kHz < fs ≤ 24kHz
10
1
0
24kHz < fs ≤ 48kHz
12
1
1
0
0
0
1024fs
7.35kHz ≤ fs ≤ 12kHz
Others
Others
N/A
N/A
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (N/A: Not Available)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through HPL/HPR pins is shown in Table 15.
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
256fs
83 dB
384fs
83 dB
512fs
95 dB
1024fs
96 dB
Table 15. Relationship between MCKI and S/N of LOUT/ROUT pins
AK4953A
MCKO
MCKI
B IC K
LRCK
SDTO
SDTI
256fs, 384fs,
512fs or 1024fs
32fs or 64fs
1fs
DSP or μP
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 18. EXT Master Mode
BCKO bit BICK Output Frequency
0
32fs
(default)
1
64fs
Table 16. BICK Output Frequency at Master Mode
MS1252-E-00
- 30 -
2010/10