AK4953A Datasheet, PDF (58/96 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4953A]
■ Serial Control Interface
(1) 3-wire Serial Control Mode
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTIO). The data on this
interface consists of Read/Write, Register address (MSB first, 7bits) and Control or Output data (MSB first, 8bits). Each
bit is clocked in on the rising edge (“↑”) of CCLK. Data writings become available on the rising edge of CSN. When
reading the data, the CDTIO pin changes to output mode at the falling edge of 8^th CCLK and outputs D7-D0. However
this reading function is available only when READ bit = “1”. When READ bit = “0”, the CDTIO pin stays as Hi-Z even
after the falling edge of 8^th CCLK. The output finishes on the rising edge of CSN. The CDTIO is placed in a Hi-Z state
except when outputting data at read operation mode. Clock speed of CCLK is 5MHz (max). The value of internal registers
are initialized by the PDN pin = “L”.
Note 52. Data reading is only available on the following addresses; 00H~19H, 1CH~25H, 30H and 32H~4FH. When
reading the address 1AH, 1BH, 26H~2FH, 31H and 50H~7FH the register values are invalid.
CSN
CCLK _{“H” or “L”}
0 _{1 2 3 4 5 6 7 8 9 10 11 12 13 14 15}
“H” or “L”
CDTIO “H” or “L”
A6 A5 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 “H” or “L”
R/W:
A6-A0:
D7-D0:
READ/WRITE (“1”: WRITE, “0”: READ)
Register Address
Control data (Input) at Write Command
Output data (Output) at Read Command
Figure 40. Serial Control I/F Timing
MS1252-E-00
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