AK5701KN_17 Datasheet, PDF (8/64 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP内蔵16-Bit Stereo ADC

[AK5701]
スイッチング特性
(Ta=25C; AVDD=2.4  3.6V; DVDD=1.6  3.6V; C_L=20pF)
Parameter
Symbol
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
MCKO Output Timing
Frequency
fMCK
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
256fs at fs=32kHz, 29.4kHz
dMCK
LRCK Output Timing
Frequency
Except DSP Mode 1
fs
DSP Mode 1 (Note 18)
fsd
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
BCLK Output Timing
Period
BCKO1-0 bit = “01”
tBCK
BCKO1-0 bit = “10”
tBCK
Duty Cycle
dBCK
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
Pulse Width Low
tCLKL
Pulse Width High
tCLKH
MCKO Output Timing
Frequency
fMCK
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
256fs at fs=32kHz, 29.4kHz
dMCK
EXLRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
EXBCLK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
PLL Slave Mode (PLL Reference Clock = EXLRCK pin)
EXLRCK Input Timing
Frequency
fs
DSP Mode: Pulse Width High
tLRCKH
Except DSP Mode: Duty Cycle
Duty
EXBCLK Input Timing
Period
tBCK
Pulse Width Low
tBCKL
Pulse Width High
tBCKH
Note 18. サンプリング周波数は7.35kHz  48kHzです。
Min.
11.2896
0.4/fCLK
0.4/fCLK
0.2352
40
-
7.35
14.7
-
-
-
-
-
11.2896
0.4/fCLK
0.4/fCLK
0.2352
40
-
7.35
tBCK60
45
1/(64fs)
0.4 x tBCK
0.4 x tBCK
7.35
tBCK60
45
1/(64fs)
0.4 x tBCK
0.4 x tBCK
Typ.
-
-
-
-
50
33
-
-
tBCK
50
1/(32fs)
1/(64fs)
50
-
-
-
-
50
33
-
-
-
-
-
-
-
-
-
-
-
-
Max.
Unit
27
-
-
12.288
60
-
MHz
ns
ns
MHz
%
%
48
kHz
96
kHz
-
ns
-
%
-
ns
-
ns
-
%
27
MHz
-
ns
-
ns
12.288 MHz
60
%
-
%
48
kHz
1/fs  tBCK ns
55
%
1/(32fs)
ns
-
ns
-
ns
48
kHz
1/fs  tBCK ns
55
%
1/(32fs)
ns
-
ns
-
ns
MS0404-J-04
-8-
2015/10