AK5701KN_17 Datasheet, PDF (10/64 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP内蔵16-Bit Stereo ADC

[AK5701]
Parameter
Symbol
Min.
Typ.
Max.
Unit
Audio Interface Timing (DSP Mode)
Master Mode
LRCK “” to BCLK “” (Note 19)
tDBF 0.5 x tBCK  40 0.5 x tBCK 0.5 x tBCK + 40 ns
LRCK “” to BCLK “” (Note 20)
tDBF 0.5 x tBCK  40 0.5 x tBCK 0.5 x tBCK + 40 ns
BCLK “” to SDTO (BCKP bit = “0”)
tBSD
70
-
70
ns
BCLK “” to SDTO (BCKP bit = “1”)
tBSD
70
-
70
ns
Slave Mode
EXLRCK “” to EXBCLK “” (Note 19) tLRB
0.4 x tBCK
-
-
ns
EXLRCK “” to EXBCLK “” (Note 20) tLRB
0.4 x tBCK
-
-
ns
EXBCLK “” to EXLRCK “” (Note 19) tBLR
0.4 x tBCK
-
-
ns
EXBCLK “” to EXLRCK “” (Note 20) tBLR
0.4 x tBCK
-
-
ns
EXBCLK “” to SDTO (BCKP bit = “0”) tBSD
-
-
80
ns
EXBCLK “” to SDTO (BCKP bit = “1”) tBSD
-
-
80
ns
Audio Interface Timing (Left justified & I²S)
Master Mode
BCLK “” to LRCK Edge (Note 21)
tMBLR
40
-
40
ns
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
70
-
70
ns
BCLK “” to SDTO
tBSD
70
-
70
ns
Slave Mode
EXLRCK Edge to EXBCLK “” (Note 21) tLRB
50
-
-
ns
EXBCLK “” to EXLRCK Edge (Note 21) tBLR
50
-
-
ns
EXLRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
-
-
80
ns
EXBCLK “” to SDTO
tBSD
-
-
80
ns
Note 19. MSBS, BCKP bits = “00” or “11”
Note 20. MSBS, BCKP bits = “01” or “10”
Note 21. この規格値はEXLRCKのエッジとEXBCLKの “”が重ならないように規定しています。
MS0404-J-04
- 10 -
2015/10