AK5701KN_17 Datasheet, PDF (12/64 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP内蔵16-Bit Stereo ADC

[AK5701]
■ タイミング波形
MCKI
LRCK
BCLK
MCKO
1/fCLK
VIH
VIL
tCLKH
tCLKL
1/fs
tLRCKH
tLRCKL
tBCK
50%DVDD
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCKH
tBCKL
1/fMCK
50%DVDD
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
50%DVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 2. Clock Timing (PLL/EXT Master mode)
LRCK
BCLK
(BCKP = "0")
tLRCKH
tDBF
tBCK
dBCK
50%DVDD
50%DVDD
BCLK
(BCKP = "1")
SDTO
tBSD
MSB
50%DVDD
50%DVDD
Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”)
MS0404-J-04
- 12 -
2015/10