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AK5701KN_17 Datasheet, PDF (24/64 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP内蔵16-Bit Stereo ADC | |||
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[AK5701]
â PLL Master Mode (PMPLL bit = â1â, M/S bit = â1â)
å¤é¨ãã11.2896MHz, 12MHz , 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz ã®ã¯ããã¯ã
å
¥åããå
é¨ã®PLLã«ããMCKO, BCLK, LRCKã¯ããã¯ãçæãåºåãã¾ãããã¹ã¿ã¯ããã¯åºå(MCKO)
ã¯PS1-0 bit (Table 9)ã§è¨å®ãããå¨æ³¢æ°ãåºåããMCKO bitã§ON/OFFå¯è½ã§ããBCLKåºåã¯BCKO1-0 bits
ã«ããã32fs or 64fsãé¸æãããã¨ãã§ãã¾ãã(Table 10)
AK5701
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
DSP or ïP
MCKI
MCKO
BCLK
LRCK
SDTO
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTI
Figure 19. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 9. MCKOå¨æ³¢æ° (PLLã¢ã¼ã, MCKO bit = â1â)
BCKO1 bit BCKO0 bit BCLKåºåå¨æ³¢æ°
0
0
N/A
0
1
32fs
(default)
1
0
64fs
1
1
N/A
Table 10. BCLK Output Frequency at Master Mode (N/A: Not available)
MS0404-J-04
- 24 -
2015/10
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