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AK5701KN_17 Datasheet, PDF (21/64 Pages) Asahi Kasei Microsystems – PLL & MIC-AMP内蔵16-Bit Stereo ADC | |||
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[AK5701]
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å¤é¨ã¨ã®I/Fã¢ã¼ãã¯ä»¥ä¸ã®5éãã®æ¹æ³ãããã¾ãã(Table 1 and Table 2)
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 25)
1
1
See Table 4 Figure 19
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1
0
See Table 4 Figure 20
PLL Slave Mode 2
(PLL Reference Clock: EXLRCK or EXBCLK pin)
1
0
See Table 4 Figure 21
EXT Slave Mode
0
0
x
Figure 22
EXT Master Mode (Note 26)
0
1
x
Figure 23
Note 25. PLL Master Modeã«è¨å®ããéç¨ã§ãM/S bit = â1â, PMPLL bit = â0â, MCKO bit = â1âã®ã¨ãMCKO pin
ããæ£å¸¸ã§ãªãå¨æ³¢æ°ã®ã¯ããã¯ãåºåããã¾ãã
Note 26. EXT Master Modeã§ä½¿ç¨ããå ´åãFigure 49ã®æé ã§è¨å®ãã¦ä¸ããã
Table 1. Clock Mode Setting (x: Donât care)
Mode
MCKO bit MCKO pin MCKI pin
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
PLL Slave Mode
(PLL Reference Clock: EXLRCK
or EXBCLK pin)
EXT Slave Mode
0
L
1
PS1-0 bitsã§
é¸æ
PLL3-0 bits
ã§é¸æ
0
L
1
PS1-0 bitsã§
é¸æ
PLL3-0 bits
ã§é¸æ
0
L
GND
0
L
FS1-0 bitsã§
é¸æ
EXT Master Mode
0
L
FS1-0 bitsã§
é¸æ
Note 27. PLL Master Modeã§DSP Mode 1ã®ã¨ããLRCKã¯2fsã§ãã
Table 2. Clock pins state in Clock Mode
BCLK pin,
EXBCLK pin
BCLK pin
(BCKO1-0
bitsã§é¸æ)
EXBCLK pin
(ï³ 32fs)
EXBCLK pin
(PLL3-0 bits
ã§é¸æ)
EXBCLK pin
(ï³ 32fs)
BCLK pin
(BCKO1-0
bitsã§é¸æ)
LRCK pin,
EXLRCK pin
LRCK pin
(1fs)
(Note 27)
EXLRCK pin
(1fs)
EXLRCK pin
(1fs)
EXLRCK pin
(1fs)
LRCK pin
(1fs)
â ãã¹ã¿ã¢ã¼ãã¨ã¹ã¬ã¼ãã¢ã¼ãã®åãæ¿ã
ãã¹ã¿ã¢ã¼ãã¨ã¹ã¬ã¼ãã¢ã¼ãã®åãæ¿ãã¯M/S bitã§è¡ãã¾ããâ1âã§ãã¹ã¿ã¢ã¼ããâ0âã§ã¹ã¬ã¼ãã¢ã¼ã
ã§ããAK5701ã¯ãã¯ã¼ãã¦ã³æ (PDN pin = âLâ)ãåã³ãã¯ã¼ãã¦ã³è§£é¤å¾ã¯ã¹ã¬ã¼ãã¢ã¼ãã§ãããã¯ã¼
ãã¦ã³è§£é¤å¾ãM/S bitã â1âã«å¤æ´ãããã¨ã§ãã¹ã¿ã¢ã¼ãã«ãªãã¾ãã
M/S bit
0
1
Mode
使ç¨ãããã³
Slave Mode
EXBCLK, EXLRCK
Master Mode
BCLK, LRCK
Table 3. Select Master/Salve Mode
(default)
MS0404-J-04
- 21 -
2015/10
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